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| author | Tim Northover <tnorthover@apple.com> | 2013-10-07 11:10:47 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-10-07 11:10:47 +0000 |
| commit | cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09 (patch) | |
| tree | 9d2dde8a3a23df35f617e28ab1e8a04e099f2620 /lib/Target/ARM/ARM.td | |
| parent | ae06a63be5a1279739e0c8a2006e72f4bc687d57 (diff) | |
| download | llvm-cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09.tar.gz llvm-cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09.tar.bz2 llvm-cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09.tar.xz | |
ARM: allow cortex-m0 to use hint instructions
The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have
been ported across to the v6M architecture. Fortunately, v6M seems to sit
nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it
fairly easily.
rdar://problem/15144406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARM.td')
| -rw-r--r-- | lib/Target/ARM/ARM.td | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 21d1c5b181..d839ca9c9f 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -146,9 +146,12 @@ def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", "Support ARM v6 instructions", [HasV5TEOps]>; +def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", + "Support ARM v6M instructions", + [HasV6Ops]>; def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", "Support ARM v6t2 instructions", - [HasV6Ops, FeatureThumb2]>; + [HasV6MOps, FeatureThumb2]>; def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", "Support ARM v7 instructions", [HasV6T2Ops, FeaturePerfMon]>; @@ -254,7 +257,7 @@ def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2, FeatureHasSlowFPVMLx]>; // V6M Processors. -def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM, +def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6MOps, FeatureNoARM, FeatureDB, FeatureMClass]>; // V6T2 Processors. |