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| author | Quentin Colombet <qcolombet@apple.com> | 2012-12-21 04:35:05 +0000 |
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2012-12-21 04:35:05 +0000 |
| commit | e0f1d712f656d3f958b616013f1d6008c5678949 (patch) | |
| tree | 78e7083829dc40498a18d7866ecbc38b812ad3f2 /lib/Target/ARM/ARM.td | |
| parent | b66fc293a2248564ae341f40882243dacccc42f3 (diff) | |
| download | llvm-e0f1d712f656d3f958b616013f1d6008c5678949.tar.gz llvm-e0f1d712f656d3f958b616013f1d6008c5678949.tar.bz2 llvm-e0f1d712f656d3f958b616013f1d6008c5678949.tar.xz | |
Add ARM cortex-r5 subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170840 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARM.td')
| -rw-r--r-- | lib/Target/ARM/ARM.td | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 45a65fd6f1..a76715a092 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -164,6 +164,12 @@ def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", "Cortex-A15 ARM processors", [FeatureT2XtPk, FeatureFP16, FeatureAvoidPartialCPSR]>; +def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", + "Cortex-R5 ARM processors", + [FeatureSlowFPBrcc, FeatureHWDivARM, + FeatureHasSlowFPVMLx, + FeatureAvoidPartialCPSR, + FeatureT2XtPk]>; class ProcNoItin<string Name, list<SubtargetFeature> Features> : Processor<Name, NoItineraries, Features>; @@ -248,6 +254,11 @@ def : ProcessorModel<"cortex-a9-mp", CortexA9Model, def : ProcessorModel<"cortex-a15", CortexA9Model, [ProcA15, HasV7Ops, FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS]>; +// FIXME: R5 has currently the same ProcessorModel as A8. +def : ProcessorModel<"cortex-r5", CortexA8Model, + [ProcR5, HasV7Ops, FeatureDB, + FeatureVFP3, FeatureDSPThumb2, + FeatureHasRAS]>; // V7M Processors. def : ProcNoItin<"cortex-m3", [HasV7Ops, |