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| author | JF Bastien <jfb@google.com> | 2013-07-12 23:33:03 +0000 |
|---|---|---|
| committer | JF Bastien <jfb@google.com> | 2013-07-12 23:33:03 +0000 |
| commit | 1b6f5a29ab62fd3e763983f31200b4cc69fa752b (patch) | |
| tree | 96e466e9cfd5e6c32acba50732374fb26f590405 /lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | bee07bddeaf30aba392c1abd2815cd07545ef2c0 (diff) | |
| download | llvm-1b6f5a29ab62fd3e763983f31200b4cc69fa752b.tar.gz llvm-1b6f5a29ab62fd3e763983f31200b4cc69fa752b.tar.bz2 llvm-1b6f5a29ab62fd3e763983f31200b4cc69fa752b.tar.xz | |
Fix ARM paired GPR COPY lowering
ARM paired GPR COPY was being lowered to two MOVr without CC. This
patch puts the CC back.
My test is a reduction of the case where I encountered the issue,
64-bit atomics use paired GPRs.
The issue only occurs with selectionDAG, FastISel doesn't encounter it
so I didn't bother calling it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186226 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseInstrInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 5283d7b362..d6701782a4 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -745,6 +745,9 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, if (Opc == ARM::VORRq) Mov.addReg(Src); Mov = AddDefaultPred(Mov); + // MOVr can set CC. + if (Opc == ARM::MOVr) + Mov = AddDefaultCC(Mov); } // Add implicit super-register defs and kills to the last instruction. Mov->addRegisterDefined(DestReg, TRI); |