[ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.

Patch by Artyom Skrobov.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191885 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 2 insertions, 69 deletions

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 4076e3b1b1..b4266693c1 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -11,10 +11,11 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "ARMBaseInstrInfo.h"
 #include "ARM.h"
+#include "ARMBaseInstrInfo.h"
 #include "ARMBaseRegisterInfo.h"
 #include "ARMConstantPoolValue.h"
+#include "ARMFeatures.h"
 #include "ARMHazardRecognizer.h"
 #include "ARMMachineFunctionInfo.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
@@ -513,74 +514,6 @@ bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
   return Found;
 }
 
-static bool isV8EligibleForIT(MachineInstr *MI) {
-  switch (MI->getOpcode()) {
-  default:
-    return false;
-  case ARM::tADC:
-  case ARM::tADDi3:
-  case ARM::tADDi8:
-  case ARM::tADDrSPi:
-  case ARM::tADDrr:
-  case ARM::tAND:
-  case ARM::tASRri:
-  case ARM::tASRrr:
-  case ARM::tBIC:
-  case ARM::tCMNz:
-  case ARM::tCMPi8:
-  case ARM::tCMPr:
-  case ARM::tEOR:
-  case ARM::tLDRBi:
-  case ARM::tLDRBr:
-  case ARM::tLDRHi:
-  case ARM::tLDRHr:
-  case ARM::tLDRSB:
-  case ARM::tLDRSH:
-  case ARM::tLDRi:
-  case ARM::tLDRr:
-  case ARM::tLDRspi:
-  case ARM::tLSLri:
-  case ARM::tLSLrr:
-  case ARM::tLSRri:
-  case ARM::tLSRrr:
-  case ARM::tMOVi8:
-  case ARM::tMUL:
-  case ARM::tMVN:
-  case ARM::tORR:
-  case ARM::tROR:
-  case ARM::tRSB:
-  case ARM::tSBC:
-  case ARM::tSTRBi:
-  case ARM::tSTRBr:
-  case ARM::tSTRHi:
-  case ARM::tSTRHr:
-  case ARM::tSTRi:
-  case ARM::tSTRr:
-  case ARM::tSTRspi:
-  case ARM::tSUBi3:
-  case ARM::tSUBi8:
-  case ARM::tSUBrr:
-  case ARM::tTST:
-    return true;
-// there are some "conditionally deprecated" opcodes
-  case ARM::tADDspr:
-    return MI->getOperand(2).getReg() != ARM::PC;
-  case ARM::tADDrSP:
-  case ARM::tBX:
-  case ARM::tBLXr:
-  // ADD PC, SP and BLX PC were always unpredictable,
-  // now on top of it they're deprecated
-    return MI->getOperand(0).getReg() != ARM::PC;
-  case ARM::tADDhirr:
-    return MI->getOperand(0).getReg() != ARM::PC &&
-           MI->getOperand(2).getReg() != ARM::PC;
-  case ARM::tCMPhir:
-  case ARM::tMOVr:
-    return MI->getOperand(0).getReg() != ARM::PC &&
-           MI->getOperand(1).getReg() != ARM::PC;
-  }
-}
-
 /// isPredicable - Return true if the specified instruction can be predicated.
 /// By default, this returns true for every instruction with a
 /// PredicateOperand.