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| author | Bill Wendling <isanbard@gmail.com> | 2012-08-27 22:12:44 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2012-08-27 22:12:44 +0000 |
| commit | 47aa9a2bb521994509d21179b968471531986eed (patch) | |
| tree | fdaa6e711fc6581c81dd8a240b885c8edddac363 /lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | 40e466091e76f4608ad09789546d3012c8c11c3e (diff) | |
| download | llvm-47aa9a2bb521994509d21179b968471531986eed.tar.gz llvm-47aa9a2bb521994509d21179b968471531986eed.tar.bz2 llvm-47aa9a2bb521994509d21179b968471531986eed.tar.xz | |
Make sure we add the predicate after all of the registers are added.
<rdar://problem/12183003>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162703 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseInstrInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 29033e5117..2112992dd8 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -712,11 +712,12 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing); unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing); assert(Dst && Src && "Bad sub-register"); - Mov = AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) - .addReg(Src)); + Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst) + .addReg(Src); // VORR takes two source operands. if (Opc == ARM::VORRq) Mov.addReg(Src); + Mov = AddDefaultPred(Mov); } // Add implicit super-register defs and kills to the last instruction. Mov->addRegisterDefined(DestReg, TRI); |