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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-27 23:58:52 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-27 23:58:52 +0000 |
| commit | dd364419ee64cd5bb234af006ce0cb285e4a84ca (patch) | |
| tree | 39b3a87aca20346bf316390cb68c42812ce683ab /lib/Target/ARM/ARMBaseInstrInfo.cpp | |
| parent | 94a935f072452d00207b1e8c1da75c31bb2a5f9b (diff) | |
| download | llvm-dd364419ee64cd5bb234af006ce0cb285e4a84ca.tar.gz llvm-dd364419ee64cd5bb234af006ce0cb285e4a84ca.tar.bz2 llvm-dd364419ee64cd5bb234af006ce0cb285e4a84ca.tar.xz | |
Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.
Atomic loads are also prevented from participating in rematerialization
and load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseInstrInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index 2112992dd8..378331f382 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2778,8 +2778,8 @@ static int adjustDefLatency(const ARMSubtarget &Subtarget, // variants are one cycle cheaper. switch (DefMCID->getOpcode()) { default: break; - case ARM::LDRrs: - case ARM::LDRBrs: { + case ARM::LDRrs: case ARM::ATOMIC_LDRrs: + case ARM::LDRBrs: case ARM::ATOMIC_LDRBrs: { unsigned ShOpVal = DefMI->getOperand(3).getImm(); unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); if (ShImm == 0 || @@ -2787,9 +2787,9 @@ static int adjustDefLatency(const ARMSubtarget &Subtarget, --Adjust; break; } - case ARM::t2LDRs: - case ARM::t2LDRBs: - case ARM::t2LDRHs: + case ARM::t2LDRs: case ARM::ATOMIC_t2LDRs: + case ARM::t2LDRBs: case ARM::ATOMIC_t2LDRBs: + case ARM::t2LDRHs: case ARM::ATOMIC_t2LDRHs: case ARM::t2LDRSHs: { // Thumb2 mode: lsl only. unsigned ShAmt = DefMI->getOperand(3).getImm(); @@ -3046,8 +3046,8 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, // variants are one cycle cheaper. switch (DefMCID.getOpcode()) { default: break; - case ARM::LDRrs: - case ARM::LDRBrs: { + case ARM::LDRrs: case ARM::ATOMIC_LDRrs: + case ARM::LDRBrs: case ARM::ATOMIC_LDRBrs: { unsigned ShOpVal = cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue(); unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal); @@ -3056,9 +3056,9 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, --Latency; break; } - case ARM::t2LDRs: - case ARM::t2LDRBs: - case ARM::t2LDRHs: + case ARM::t2LDRs: case ARM::ATOMIC_t2LDRs: + case ARM::t2LDRBs: case ARM::ATOMIC_t2LDRBs: + case ARM::t2LDRHs: case ARM::ATOMIC_t2LDRHs: case ARM::t2LDRSHs: { // Thumb2 mode: lsl only. unsigned ShAmt = |