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authorBill Wendling <isanbard@gmail.com>2013-06-07 05:54:19 +0000
committerBill Wendling <isanbard@gmail.com>2013-06-07 05:54:19 +0000
commit57148c166ab232191098492633c924fad9c44ef3 (patch)
tree2742791240f5d1a8babb627efc05493190cadb28 /lib/Target/ARM/ARMBaseInstrInfo.h
parent4393f48c03300203594e22d248808f20dd59d886 (diff)
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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183488 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseInstrInfo.h')
-rw-r--r--lib/Target/ARM/ARMBaseInstrInfo.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h
index 2ef659c23b..4ca3d7b411 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -46,7 +46,7 @@ public:
MachineBasicBlock::iterator &MBBI,
LiveVariables *LV) const;
- virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0;
+ virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
const ARMSubtarget &getSubtarget() const { return Subtarget; }
ScheduleHazardRecognizer *