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author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-03-31 23:26:08 +0000 |
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committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2011-03-31 23:26:08 +0000 |
commit | ae0855401b8c80f96904b6808b0bc4c89216aecd (patch) | |
tree | 9af5d7fbc7585b1555b09e35457b11f4ae9a897f /lib/Target/ARM/ARMBaseInstrInfo.h | |
parent | 842759662ba3eae35d6078643983a07266be9aa5 (diff) | |
download | llvm-ae0855401b8c80f96904b6808b0bc4c89216aecd.tar.gz llvm-ae0855401b8c80f96904b6808b0bc4c89216aecd.tar.bz2 llvm-ae0855401b8c80f96904b6808b0bc4c89216aecd.tar.xz |
Apply again changes to support ARM memory asm parsing. I removed
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseInstrInfo.h')
-rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.h | 24 |
1 files changed, 2 insertions, 22 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index 228b6cd914..30095fe735 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -34,25 +34,7 @@ namespace ARMII { //===------------------------------------------------------------------===// // This four-bit field describes the addressing mode used. - - AddrModeMask = 0x1f, - AddrModeNone = 0, - AddrMode1 = 1, - AddrMode2 = 2, - AddrMode3 = 3, - AddrMode4 = 4, - AddrMode5 = 5, - AddrMode6 = 6, - AddrModeT1_1 = 7, - AddrModeT1_2 = 8, - AddrModeT1_4 = 9, - AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data - AddrModeT2_i12 = 11, - AddrModeT2_i8 = 12, - AddrModeT2_so = 13, - AddrModeT2_pc = 14, // +/- i12 for pc relative data - AddrModeT2_i8s4 = 15, // i8 * 4 - AddrMode_i12 = 16, + AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h // Size* - Flags to keep track of the size of an instruction. SizeShift = 5, @@ -64,11 +46,9 @@ namespace ARMII { // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load // and store ops only. Generic "updating" flag is used for ld/st multiple. + // The index mode enums are declared in ARMBaseInfo.h IndexModeShift = 8, IndexModeMask = 3 << IndexModeShift, - IndexModePre = 1, - IndexModePost = 2, - IndexModeUpd = 3, //===------------------------------------------------------------------===// // Instruction encoding formats. |