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| author | Lang Hames <lhames@gmail.com> | 2012-03-06 00:19:55 +0000 |
|---|---|---|
| committer | Lang Hames <lhames@gmail.com> | 2012-03-06 00:19:55 +0000 |
| commit | 4f92b5e6163b16d63eb63269c2aec670b55ea19a (patch) | |
| tree | 964b85f11ba8de9367f99501d06a22d7f7166755 /lib/Target/ARM/ARMBaseRegisterInfo.cpp | |
| parent | 923bb4117a13eac03a6ff630a108829ab767d519 (diff) | |
| download | llvm-4f92b5e6163b16d63eb63269c2aec670b55ea19a.tar.gz llvm-4f92b5e6163b16d63eb63269c2aec670b55ea19a.tar.bz2 llvm-4f92b5e6163b16d63eb63269c2aec670b55ea19a.tar.xz | |
Split fpscr into two registers: FPSCR and FPSCR_NZCV.
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index d2aff9a87b..6a4c21d1d3 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -79,6 +79,7 @@ getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); Reserved.set(ARM::SP); Reserved.set(ARM::PC); + Reserved.set(ARM::FPSCR); if (TFI->hasFP(MF)) Reserved.set(FramePtr); if (hasBasePointer(MF)) |