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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-28 03:11:27 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-28 03:11:27 +0000 |
| commit | cff9baa95273bc279bf5fadb9e27afbd25cca20b (patch) | |
| tree | 730875c1eeb110a771f0879c8371beca62adf957 /lib/Target/ARM/ARMBaseRegisterInfo.cpp | |
| parent | 273956d8c6eed86c8b4d616ecb86f7ff17e127d4 (diff) | |
| download | llvm-cff9baa95273bc279bf5fadb9e27afbd25cca20b.tar.gz llvm-cff9baa95273bc279bf5fadb9e27afbd25cca20b.tar.bz2 llvm-cff9baa95273bc279bf5fadb9e27afbd25cca20b.tar.xz | |
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM."
This wasn't the right way to enforce ordering of atomics.
We are already setting the isVolatile bit on memory operands of atomic
operations which is good enough to enforce the correct ordering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162732 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 828e7d4e95..9deb96ea9e 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -870,14 +870,10 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { // return false for everything else. unsigned Opc = MI->getOpcode(); switch (Opc) { - case ARM::LDRi12: case ARM::ATOMIC_LDRi12: - case ARM::LDRH: case ARM::ATOMIC_LDRH: - case ARM::LDRBi12: case ARM::ATOMIC_LDRBi12: + case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: - case ARM::t2LDRi12: case ARM::ATOMIC_t2LDRi12: - case ARM::t2LDRi8: case ARM::ATOMIC_t2LDRi8: - case ARM::t2STRi12: - case ARM::t2STRi8: + case ARM::t2LDRi12: case ARM::t2LDRi8: + case ARM::t2STRi12: case ARM::t2STRi8: case ARM::VLDRS: case ARM::VLDRD: case ARM::VSTRS: case ARM::VSTRD: case ARM::tSTRspi: case ARM::tLDRspi: |