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author | Jim Grosbach <grosbach@apple.com> | 2010-10-27 17:52:51 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2010-10-27 17:52:51 +0000 |
commit | 093177d5cde06dcb63829320f12195c32485a6d1 (patch) | |
tree | c37a9c0e2c1fcebae7615626053226a9e45cac8c /lib/Target/ARM/ARMCodeEmitter.cpp | |
parent | 633919c79a86e36b26fb62007731341a31f2188d (diff) | |
download | llvm-093177d5cde06dcb63829320f12195c32485a6d1.tar.gz llvm-093177d5cde06dcb63829320f12195c32485a6d1.tar.bz2 llvm-093177d5cde06dcb63829320f12195c32485a6d1.tar.xz |
The new LDR* instruction patterns should handle the necessary encoding of
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMCodeEmitter.cpp')
-rw-r--r-- | lib/Target/ARM/ARMCodeEmitter.cpp | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index edb9c906b1..0ff0d5142a 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -946,6 +946,13 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); + // If this is an LDRi12, LDRrs, or LDRcp, nothing more needs be done. + if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRrs + || MI.getOpcode() == ARM::LDRcp) { + emitWordLE(Binary); + return; + } + // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; |