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| author | Bob Wilson <bob.wilson@apple.com> | 2011-08-13 05:14:55 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2011-08-13 05:14:55 +0000 |
| commit | 7dcd04abe0b0b1dbfb285faea2daece50f9aa502 (patch) | |
| tree | ebca6f2095da1dc75aea8adeabef7be3b794ce31 /lib/Target/ARM/ARMExpandPseudoInsts.cpp | |
| parent | 53b2b7364385b2f2d98c0052df73a637a81c2288 (diff) | |
| download | llvm-7dcd04abe0b0b1dbfb285faea2daece50f9aa502.tar.gz llvm-7dcd04abe0b0b1dbfb285faea2daece50f9aa502.tar.bz2 llvm-7dcd04abe0b0b1dbfb285faea2daece50f9aa502.tar.xz | |
Expand VMOVQQQQ pseudo instructions.
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed. Our register allocator must be awesome!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137551 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMExpandPseudoInsts.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index a4fcfd51bf..a1be94ab87 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -998,6 +998,52 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, return true; } + case ARM::VMOVQQQQ: { + unsigned DstReg = MI.getOperand(0).getReg(); + bool DstIsDead = MI.getOperand(0).isDead(); + unsigned Dst0 = TRI->getSubReg(DstReg, ARM::qsub_0); + unsigned Dst1 = TRI->getSubReg(DstReg, ARM::qsub_1); + unsigned Dst2 = TRI->getSubReg(DstReg, ARM::qsub_2); + unsigned Dst3 = TRI->getSubReg(DstReg, ARM::qsub_3); + unsigned SrcReg = MI.getOperand(1).getReg(); + bool SrcIsKill = MI.getOperand(1).isKill(); + unsigned Src0 = TRI->getSubReg(SrcReg, ARM::qsub_0); + unsigned Src1 = TRI->getSubReg(SrcReg, ARM::qsub_1); + unsigned Src2 = TRI->getSubReg(SrcReg, ARM::qsub_2); + unsigned Src3 = TRI->getSubReg(SrcReg, ARM::qsub_3); + MachineInstrBuilder Mov0 = + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::VORRq)) + .addReg(Dst0, + RegState::Define | getDeadRegState(DstIsDead)) + .addReg(Src0, getKillRegState(SrcIsKill)) + .addReg(Src0, getKillRegState(SrcIsKill))); + MachineInstrBuilder Mov1 = + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::VORRq)) + .addReg(Dst1, + RegState::Define | getDeadRegState(DstIsDead)) + .addReg(Src1, getKillRegState(SrcIsKill)) + .addReg(Src1, getKillRegState(SrcIsKill))); + MachineInstrBuilder Mov2 = + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::VORRq)) + .addReg(Dst2, + RegState::Define | getDeadRegState(DstIsDead)) + .addReg(Src2, getKillRegState(SrcIsKill)) + .addReg(Src2, getKillRegState(SrcIsKill))); + MachineInstrBuilder Mov3 = + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(ARM::VORRq)) + .addReg(Dst3, + RegState::Define | getDeadRegState(DstIsDead)) + .addReg(Src3, getKillRegState(SrcIsKill)) + .addReg(Src3, getKillRegState(SrcIsKill))); + TransferImpOps(MI, Mov0, Mov3); + MI.eraseFromParent(); + return true; + } + case ARM::VLDMQIA: { unsigned NewOpc = ARM::VLDMDIA; MachineInstrBuilder MIB = |