| Commit message (Expand) | Author | Age |
|---|
| * | Merging r199369: | Tom Stellard | 2014-04-09 |
| * | ARM: preserve undef flag in pseudo instruction expanders | Matthias Braun | 2013-10-04 |
| * | ARM: support interrupt attribute | Tim Northover | 2013-10-01 |
| * | Even more spelling fixes for "instruction". | Robert Wilhelm | 2013-09-28 |
| * | ARM: use TableGen patterns to select CMOV operations. | Tim Northover | 2013-08-22 |
| * | Use the new script to sort the includes of every file under lib. | Chandler Carruth | 2012-12-03 |
| * | Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all | Chad Rosier | 2012-11-06 |
| * | Revert r163298 "Optimize codegen for VSETLNi{8,16,32} operating on Q registers." | Jakob Stoklund Olesen | 2012-10-26 |
| * | Change enum type in a static table to uint8_t instead. Saves about 700 hundre... | Craig Topper | 2012-09-20 |
| * | Optimize codegen for VSETLNi{8,16,32} operating on Q registers. Degenerate to... | James Molloy | 2012-09-06 |
| * | Remove getARMRegisterNumbering and replace with calls into | Eric Christopher | 2012-08-09 |
| * | Preserve <undef> flags in ARMExpandPseudo. | Jakob Stoklund Olesen | 2012-06-15 |
| * | Transfer memory operands to the right instruction. | Jakob Stoklund Olesen | 2012-05-20 |
| * | Remove unnecessary llvm:: qualifications | Craig Topper | 2012-03-27 |
| * | Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h | Craig Topper | 2012-03-26 |
| * | Use uint16_t to store registers and opcode in static tables in the target spe... | Craig Topper | 2012-03-11 |
| * | ARM refactor more NEON VLD/VST instructions to use composite physregs | Jim Grosbach | 2012-03-06 |
| * | ARM refactor away a bunch of VLD/VST pseudo instructions. | Jim Grosbach | 2012-03-05 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 |
| * | More dead code removal (using -Wunreachable-code) | David Blaikie | 2012-01-20 |
| * | ARM updating VST2 pseudo-lowering fixed vs. register update. | Jim Grosbach | 2012-01-10 |
| * | Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138> | Bob Wilson | 2011-12-22 |
| * | ARM NEON assmebly parsing for VLD2 to all lanes instructions. | Jim Grosbach | 2011-12-21 |
| * | ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. | Jim Grosbach | 2011-12-21 |
| * | Preserve more memory operands in ARMExpandPseudo. | Jakob Stoklund Olesen | 2011-12-17 |
| * | ARM NEON VTBL/VTBX assembly parsing and encoding. | Jim Grosbach | 2011-12-15 |
| * | ARM NEON refactor VST2 w/ writeback instructions. | Jim Grosbach | 2011-12-14 |
| * | ARM NEON VST2 assembly parsing and encoding. | Jim Grosbach | 2011-12-14 |
| * | ARM assembly parsing and encoding for VLD2 with writeback. | Jim Grosbach | 2011-12-09 |
| * | ARM parsing for VLD1 all lanes, with writeback. | Jim Grosbach | 2011-11-30 |
| * | ARM parsing for VLD1 two register all lanes, no writeback. | Jim Grosbach | 2011-11-30 |
| * | ARM assembly parsing and encoding for four-register VST1. | Jim Grosbach | 2011-11-29 |
| * | ARM assembly parsing and encoding for three-register VST1. | Jim Grosbach | 2011-11-29 |
| * | Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602> | Bob Wilson | 2011-11-16 |
| * | Re-apply 144430, this time with the associated isel and disassmbler bits. | Jim Grosbach | 2011-11-12 |
| * | ARM VST1 w/ writeback assembly parsing and encoding. | Jim Grosbach | 2011-10-31 |
| * | ARM writeback vs. stride operands for VST/VLD. | Jim Grosbach | 2011-10-31 |
| * | Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction. | Jim Grosbach | 2011-10-24 |
| * | ARM assembly parsing and encoding for VLD1 w/ writeback. | Jim Grosbach | 2011-10-24 |
| * | ARM refactor am6offset usage for VLD1. | Jim Grosbach | 2011-10-24 |
| * | Assembly parsing for 4-register sequential variant of VLD2. | Jim Grosbach | 2011-10-21 |
| * | Assembly parsing for 2-register sequential variant of VLD2. | Jim Grosbach | 2011-10-21 |
| * | Assembly parsing for 4-register variant of VLD1. | Jim Grosbach | 2011-10-21 |
| * | Assembly parsing for 3-register variant of VLD1. | Jim Grosbach | 2011-10-21 |
| * | ARM VLD parsing and encoding. | Jim Grosbach | 2011-10-21 |
| * | Tidy up. Formatting. | Jim Grosbach | 2011-09-02 |
| * | Remove the VMOVQQ pseudo instruction. | Chad Rosier | 2011-08-20 |
| * | VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg. | Chad Rosier | 2011-08-20 |
| * | Make a bunch of symbols private. | Benjamin Kramer | 2011-08-19 |
| * | Expand VMOVQQQQ pseudo instructions. | Bob Wilson | 2011-08-13 |
