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| author | Chad Rosier <mcrosier@apple.com> | 2011-08-20 00:52:40 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2011-08-20 00:52:40 +0000 |
| commit | fea95c6bade86fcfa5bd07efdda9bd902f53be8c (patch) | |
| tree | de65a483a24118331fc17735f1eef95704ee3265 /lib/Target/ARM/ARMExpandPseudoInsts.cpp | |
| parent | cbb9905d961aeec0a90a95a594d5c938dfe1f253 (diff) | |
| download | llvm-fea95c6bade86fcfa5bd07efdda9bd902f53be8c.tar.gz llvm-fea95c6bade86fcfa5bd07efdda9bd902f53be8c.tar.bz2 llvm-fea95c6bade86fcfa5bd07efdda9bd902f53be8c.tar.xz | |
Remove the VMOVQQ pseudo instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138177 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMExpandPseudoInsts.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 52c8ab7e18..89918f9183 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -970,34 +970,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, ExpandMOV32BitImm(MBB, MBBI); return true; - case ARM::VMOVQQ: { - unsigned DstReg = MI.getOperand(0).getReg(); - bool DstIsDead = MI.getOperand(0).isDead(); - unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0); - unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1); - unsigned SrcReg = MI.getOperand(1).getReg(); - bool SrcIsKill = MI.getOperand(1).isKill(); - unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0); - unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1); - MachineInstrBuilder Even = - AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), - TII->get(ARM::VORRq)) - .addReg(EvenDst, - RegState::Define | getDeadRegState(DstIsDead)) - .addReg(EvenSrc, getKillRegState(SrcIsKill)) - .addReg(EvenSrc, getKillRegState(SrcIsKill))); - MachineInstrBuilder Odd = - AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), - TII->get(ARM::VORRq)) - .addReg(OddDst, - RegState::Define | getDeadRegState(DstIsDead)) - .addReg(OddSrc, getKillRegState(SrcIsKill)) - .addReg(OddSrc, getKillRegState(SrcIsKill))); - TransferImpOps(MI, Even, Odd); - MI.eraseFromParent(); - return true; - } - case ARM::VLDMQIA: { unsigned NewOpc = ARM::VLDMDIA; MachineInstrBuilder MIB = |