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| author | Bob Wilson <bob.wilson@apple.com> | 2010-12-13 21:05:52 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-12-13 21:05:52 +0000 |
| commit | 3a6756cb1c87908f5d04660b6ed7d464b56f78f6 (patch) | |
| tree | 21b1dcb84a86c5c2b548ca6ad00f762459da473f /lib/Target/ARM/ARMExpandPseudoInsts.cpp | |
| parent | 6dbcea1f8e557a5374714338f9b5116ae139ef32 (diff) | |
| download | llvm-3a6756cb1c87908f5d04660b6ed7d464b56f78f6.tar.gz llvm-3a6756cb1c87908f5d04660b6ed7d464b56f78f6.tar.bz2 llvm-3a6756cb1c87908f5d04660b6ed7d464b56f78f6.tar.xz | |
Use pseudo instructions for 2-register Neon instructions for scalar FP.
Partial fix for Radar 8711675.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121716 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMExpandPseudoInsts.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 41 |
1 files changed, 29 insertions, 12 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 99ced50a19..79ca3fc50e 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -54,6 +54,7 @@ namespace { void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); void ExpandVTBL(MachineBasicBlock::iterator &MBBI, unsigned Opc, bool IsExt, unsigned NumRegs); + void ExpandNeonSFP2(MachineBasicBlock::iterator &MBBI, unsigned Opc); }; char ARMExpandPseudo::ID = 0; } @@ -612,6 +613,21 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, MI.eraseFromParent(); } +/// ExpandNeonSFP2 - Translate a 2-register Neon pseudo instruction used for +/// scalar floating-point to a real instruction. +void ARMExpandPseudo::ExpandNeonSFP2(MachineBasicBlock::iterator &MBBI, + unsigned Opc) { + MachineInstr &MI = *MBBI; + MachineBasicBlock &MBB = *MI.getParent(); + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); + MIB.addOperand(MI.getOperand(0)) // destination register + .addOperand(MI.getOperand(1)) // source register + .addOperand(MI.getOperand(2)) // predicate + .addOperand(MI.getOperand(3)); // predicate register + TransferImpOps(MI, MIB, MIB); + MI.eraseFromParent(); +} + bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { bool Modified = false; @@ -1145,18 +1161,19 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { ExpandLaneOp(MBBI); break; - case ARM::VTBL2Pseudo: - ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break; - case ARM::VTBL3Pseudo: - ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break; - case ARM::VTBL4Pseudo: - ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break; - case ARM::VTBX2Pseudo: - ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break; - case ARM::VTBX3Pseudo: - ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break; - case ARM::VTBX4Pseudo: - ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break; + case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); break; + case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); break; + case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); break; + case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); break; + case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); break; + case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); break; + + case ARM::VABSfd_sfp: ExpandNeonSFP2(MBBI, ARM::VABSfd); break; + case ARM::VNEGfd_sfp: ExpandNeonSFP2(MBBI, ARM::VNEGfd); break; + case ARM::VCVTf2sd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTf2sd); break; + case ARM::VCVTf2ud_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTf2ud); break; + case ARM::VCVTs2fd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTs2fd); break; + case ARM::VCVTu2fd_sfp: ExpandNeonSFP2(MBBI, ARM::VCVTu2fd); break; } if (ModifiedOp) |