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| author | Owen Anderson <resistor@mac.com> | 2011-02-08 22:39:40 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-02-08 22:39:40 +0000 |
| commit | 971b83b67a9812556cdb97bb58aa96fb37af458d (patch) | |
| tree | f930f489860440e92e4bc792b16ac97c96583303 /lib/Target/ARM/ARMExpandPseudoInsts.cpp | |
| parent | 0fd90bc12f77820e757ef3a427fab9f66aba6381 (diff) | |
| download | llvm-971b83b67a9812556cdb97bb58aa96fb37af458d.tar.gz llvm-971b83b67a9812556cdb97bb58aa96fb37af458d.tar.bz2 llvm-971b83b67a9812556cdb97bb58aa96fb37af458d.tar.xz | |
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMExpandPseudoInsts.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 43 |
1 files changed, 5 insertions, 38 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index e0aeb920af..bd753d29ab 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -780,7 +780,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, return true; } case ARM::TPsoft: { - MachineInstrBuilder MIB = + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL)) .addExternalSymbol("__aeabi_read_tp", 0); @@ -790,49 +790,16 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, MI.eraseFromParent(); return true; } - case ARM::t2LDRHpci: - case ARM::t2LDRBpci: - case ARM::t2LDRSHpci: - case ARM::t2LDRSBpci: - case ARM::t2LDRpci: { - unsigned NewLdOpc; - if (Opcode == ARM::t2LDRpci) - NewLdOpc = ARM::t2LDRi12; - else if (Opcode == ARM::t2LDRHpci) - NewLdOpc = ARM::t2LDRHi12; - else if (Opcode == ARM::t2LDRBpci) - NewLdOpc = ARM::t2LDRBi12; - else if (Opcode == ARM::t2LDRSHpci) - NewLdOpc = ARM::t2LDRSHi12; - else if (Opcode == ARM::t2LDRSBpci) - NewLdOpc = ARM::t2LDRSBi12; - else - llvm_unreachable("Not a known opcode?"); - - unsigned DstReg = MI.getOperand(0).getReg(); - MachineInstrBuilder MIB = - AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), - TII->get(NewLdOpc), DstReg) - .addReg(ARM::PC) - .addOperand(MI.getOperand(1))); - (*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); - TransferImpOps(MI, MIB, MIB); - MI.eraseFromParent(); - return true; - } - case ARM::tLDRpci_pic: case ARM::t2LDRpci_pic: { unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) - ? ARM::tLDRpci : ARM::t2LDRi12; + ? ARM::tLDRpci : ARM::t2LDRpci; unsigned DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); MachineInstrBuilder MIB1 = - BuildMI(MBB, MBBI, MI.getDebugLoc(), - TII->get(NewLdOpc), DstReg); - if (Opcode == ARM::t2LDRpci_pic) MIB1.addReg(ARM::PC); - MIB1.addOperand(MI.getOperand(1)); - AddDefaultPred(MIB1); + AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(NewLdOpc), DstReg) + .addOperand(MI.getOperand(1))); (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) |