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| author | Bob Wilson <bob.wilson@apple.com> | 2011-12-22 23:39:48 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2011-12-22 23:39:48 +0000 |
| commit | f4aea8f34946d4d2b101b8e3c6db95c18be80173 (patch) | |
| tree | 7bca960b011b52d1bfb36e07768c3615ca38247f /lib/Target/ARM/ARMExpandPseudoInsts.cpp | |
| parent | bfbc9fcb8330e00f5fd6d1a52131950eb69be934 (diff) | |
| download | llvm-f4aea8f34946d4d2b101b8e3c6db95c18be80173.tar.gz llvm-f4aea8f34946d4d2b101b8e3c6db95c18be80173.tar.bz2 llvm-f4aea8f34946d4d2b101b8e3c6db95c18be80173.tar.xz | |
Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>
My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used. This
caused massive failures on the testsuite when compiling for Thumb1. While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147204 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMExpandPseudoInsts.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 1fb769754c..35f3c25500 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -842,7 +842,9 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, MI.eraseFromParent(); return true; } - case ARM::eh_sjlj_dispatchsetup: { + case ARM::Int_eh_sjlj_dispatchsetup: + case ARM::Int_eh_sjlj_dispatchsetup_nofp: + case ARM::tInt_eh_sjlj_dispatchsetup: { MachineFunction &MF = *MI.getParent()->getParent(); const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII); |