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author | Chad Rosier <mcrosier@apple.com> | 2011-11-05 20:16:15 +0000 |
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committer | Chad Rosier <mcrosier@apple.com> | 2011-11-05 20:16:15 +0000 |
commit | 42536af5ce152593f489ca88bd0732218594d536 (patch) | |
tree | c543f6ecc7b337d0fa8528129dc1dfbcbe7227dd /lib/Target/ARM/ARMFastISel.cpp | |
parent | 7494a12a65b13f7857d6be8d08bc159b614cbfbd (diff) | |
download | llvm-42536af5ce152593f489ca88bd0732218594d536.tar.gz llvm-42536af5ce152593f489ca88bd0732218594d536.tar.bz2 llvm-42536af5ce152593f489ca88bd0732218594d536.tar.xz |
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143821 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMFastISel.cpp')
-rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 44 |
1 files changed, 16 insertions, 28 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 517f73f4e1..c98156e886 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -557,7 +557,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) { unsigned ImmReg = createResultReg(TLI.getRegClassFor(SrcVT)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ImmReg) - .addImm(CI->getSExtValue())); + .addImm(CI->getZExtValue())); return ImmReg; } @@ -1599,33 +1599,21 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args, switch (VA.getLocInfo()) { case CCValAssign::Full: break; case CCValAssign::SExt: { - bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), - Arg, ArgVT, Arg); - assert(Emitted && "Failed to emit a sext!"); (void)Emitted; - Emitted = true; - ArgVT = VA.getLocVT(); + EVT DestVT = VA.getLocVT(); + unsigned ResultReg = ARMEmitIntExt(ArgVT, Arg, DestVT, + /*isZExt*/false); + assert (ResultReg != 0 && "Failed to emit a sext"); + Arg = ResultReg; break; } + case CCValAssign::AExt: + // Intentional fall-through. Handle AExt and ZExt. case CCValAssign::ZExt: { - bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), - Arg, ArgVT, Arg); - assert(Emitted && "Failed to emit a zext!"); (void)Emitted; - Emitted = true; - ArgVT = VA.getLocVT(); - break; - } - case CCValAssign::AExt: { - bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), - Arg, ArgVT, Arg); - if (!Emitted) - Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), - Arg, ArgVT, Arg); - if (!Emitted) - Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), - Arg, ArgVT, Arg); - - assert(Emitted && "Failed to emit a aext!"); (void)Emitted; - ArgVT = VA.getLocVT(); + EVT DestVT = VA.getLocVT(); + unsigned ResultReg = ARMEmitIntExt(ArgVT, Arg, DestVT, + /*isZExt*/true); + assert (ResultReg != 0 && "Failed to emit a sext"); + Arg = ResultReg; break; } case CCValAssign::BCvt: { @@ -1643,7 +1631,7 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args, if (VA.isRegLoc() && !VA.needsCustom()) { BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), VA.getLocReg()) - .addReg(Arg); + .addReg(Arg); RegArgs.push_back(VA.getLocReg()); } else if (VA.needsCustom()) { // TODO: We need custom lowering for vector (v2f64) args. @@ -1962,8 +1950,8 @@ bool ARMFastISel::SelectCall(const Instruction *I) { Type *ArgTy = (*i)->getType(); MVT ArgVT; - // FIXME: Should be able to handle i1, i8, and/or i16 parameters. - if (!isTypeLegal(ArgTy, ArgVT)) + if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 && + ArgVT != MVT::i1) return false; unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); Flags.setOrigAlign(OriginalAlignment); |