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| author | Bob Wilson <bob.wilson@apple.com> | 2011-12-04 00:52:23 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2011-12-04 00:52:23 +0000 |
| commit | 6ce2deacefa5fd2565983d513d07a06d6a8af602 (patch) | |
| tree | a98d54f37cb1f72c979fab48baf9bd0280f127fb /lib/Target/ARM/ARMFastISel.cpp | |
| parent | 0cb2a45cceaefb48ec7efb902c453aaae4e24cb2 (diff) | |
| download | llvm-6ce2deacefa5fd2565983d513d07a06d6a8af602.tar.gz llvm-6ce2deacefa5fd2565983d513d07a06d6a8af602.tar.bz2 llvm-6ce2deacefa5fd2565983d513d07a06d6a8af602.tar.xz | |
Fix 80-column issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145783 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMFastISel.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 63f3d45487..ea03fb7a60 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -181,7 +181,8 @@ class ARMFastISel : public FastISel { bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, bool isZExt, bool allocReg); - bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, unsigned Alignment = 0); + bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, + unsigned Alignment = 0); bool ARMComputeAddress(const Value *Obj, Address &Addr); void ARMSimplifyAddress(Address &Addr, EVT VT, bool useAM3); bool ARMIsMemCpySmall(uint64_t Len); @@ -937,7 +938,8 @@ void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr, // Now add the rest of the operands. MIB.addFrameIndex(FI); - // ARM halfword load/stores and signed byte loads need an additional operand. + // ARM halfword load/stores and signed byte loads need an additional + // operand. if (useAM3) { signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; MIB.addReg(0); @@ -950,7 +952,8 @@ void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr, // Now add the rest of the operands. MIB.addReg(Addr.Base.Reg); - // ARM halfword load/stores and signed byte loads need an additional operand. + // ARM halfword load/stores and signed byte loads need an additional + // operand. if (useAM3) { signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; MIB.addReg(0); @@ -1053,7 +1056,8 @@ bool ARMFastISel::SelectLoad(const Instruction *I) { return true; } -bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, unsigned Alignment) { +bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, + unsigned Alignment) { unsigned StrOpc; bool useAM3 = false; switch (VT.getSimpleVT().SimpleTy) { |