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authorBill Wendling <isanbard@gmail.com>2011-10-18 22:52:20 +0000
committerBill Wendling <isanbard@gmail.com>2011-10-18 22:52:20 +0000
commit85f3a0a4c4c1953a06ea463c6b5d6b88d62b58b4 (patch)
treeadcf36a899632e27f19e08c0a222fd358af9b091 /lib/Target/ARM/ARMISelLowering.cpp
parent7e8ae57be914cbb6fab111d98a89c6f07c77d2a1 (diff)
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Use the integer compare when the value is small enough. Use the "move into a
register and then compare against that" method when it's too large. We have to move the value into the register in the "movw, movt" pair of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142440 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp19
1 files changed, 17 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 759d3b6e0d..236ea6f90a 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -5672,9 +5672,7 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
MachineRegisterInfo *MRI = &MF->getRegInfo();
ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
MachineFrameInfo *MFI = MF->getFrameInfo();
- MachineConstantPool *MCP = MF->getConstantPool();
int FI = MFI->getFunctionContextIndex();
- const Function *F = MF->getFunction();
const TargetRegisterClass *TRC =
Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
@@ -5863,6 +5861,23 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
.addImm(4)
.addMemOperand(FIMMOLd));
+ if (NumLPads < 256) {
+ AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
+ .addReg(NewVReg1)
+ .addImm(NumLPads));
+ } else {
+ unsigned VReg1 = MRI->createVirtualRegister(TRC);
+ AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
+ .addImm(NumLPads & 0xFF));
+ unsigned VReg2 = MRI->createVirtualRegister(TRC);
+ AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
+ .addReg(VReg1)
+ .addImm(NumLPads >> 16));
+ AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
+ .addReg(NewVReg1)
+ .addReg(VReg2));
+ }
+
unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), NewVReg2)
.addImm(LPadList.size()));