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author | Evan Cheng <evan.cheng@apple.com> | 2007-01-31 08:40:13 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-01-31 08:40:13 +0000 |
commit | b6ab2547cb4e4c7b237d88ad11316a69b111f88e (patch) | |
tree | 46bcca14da1f1571391dff045d796593c60f6c57 /lib/Target/ARM/ARMISelLowering.cpp | |
parent | b85210f508556a81aecde07b87b2dfc6236de6e7 (diff) | |
download | llvm-b6ab2547cb4e4c7b237d88ad11316a69b111f88e.tar.gz llvm-b6ab2547cb4e4c7b237d88ad11316a69b111f88e.tar.bz2 llvm-b6ab2547cb4e4c7b237d88ad11316a69b111f88e.tar.xz |
Observe -soft-float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33699 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 0b1c3ac629..5cbf296014 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -28,6 +28,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SSARegMap.h" +#include "llvm/Target/TargetOptions.h" #include "llvm/ADT/VectorExtras.h" using namespace llvm; @@ -36,7 +37,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) Subtarget = &TM.getSubtarget<ARMSubtarget>(); // Uses VFP for Thumb libfuncs if available. - if (Subtarget->isThumb() && Subtarget->hasVFP2()) { + if (!UseSoftFloat && Subtarget->isThumb() && Subtarget->hasVFP2()) { // Single-precision floating-point arithmetic. setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); @@ -91,7 +92,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) } addRegisterClass(MVT::i32, ARM::GPRRegisterClass); - if (Subtarget->hasVFP2() && !Subtarget->isThumb()) { + if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { addRegisterClass(MVT::f32, ARM::SPRRegisterClass); addRegisterClass(MVT::f64, ARM::DPRRegisterClass); } @@ -173,7 +174,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) } setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); - if (Subtarget->hasVFP2() && !Subtarget->isThumb()) + if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) // Turn f64->i64 into FMRRD iff target supports vfp2. setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); |