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authorJim Grosbach <grosbach@apple.com>2010-11-29 18:37:44 +0000
committerJim Grosbach <grosbach@apple.com>2010-11-29 18:37:44 +0000
commit2dc7768d73c9afa3a23b86ee7827bc8de426f459 (patch)
tree3c3846d941fd37bf7b6cd065096388017450853a /lib/Target/ARM/ARMInstrFormats.td
parent5fae2f1dbb8345e6fc3232f4732acaf9b64edd90 (diff)
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Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120303 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrFormats.td')
-rw-r--r--lib/Target/ARM/ARMInstrFormats.td18
1 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index d6f9781ea4..a5f89d6e49 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -508,6 +508,24 @@ class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
let Inst{15-12} = Rt; // Rt
let Inst{7-4} = op;
}
+class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
+ IndexMode im, Format f, InstrItinClass itin, string opc,
+ string asm, string cstr, list<dag> pattern>
+ : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
+ pattern> {
+ // AM3 store w/ two operands: (GPR, am3offset)
+ bits<14> offset;
+ bits<4> Rt;
+ bits<4> Rn;
+ let Inst{27-25} = 0b000;
+ let Inst{23} = offset{8};
+ let Inst{22} = offset{9};
+ let Inst{19-16} = Rn;
+ let Inst{15-12} = Rt; // Rt
+ let Inst{11-8} = offset{7-4}; // imm7_4/zero
+ let Inst{7-4} = op;
+ let Inst{3-0} = offset{3-0}; // imm3_0/Rm
+}
// stores
class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,