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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-15 22:16:39 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-15 22:16:39 +0000 |
| commit | 2860b7ea3a1d60213ee7228bd274bc4f8b170772 (patch) | |
| tree | b01f0e59fa7da8121848824f06495d6a0509f57c /lib/Target/ARM/ARMInstrInfo.td | |
| parent | 8dd2e5bf8331f55e099763bab2b95f7509649b84 (diff) | |
| download | llvm-2860b7ea3a1d60213ee7228bd274bc4f8b170772.tar.gz llvm-2860b7ea3a1d60213ee7228bd274bc4f8b170772.tar.bz2 llvm-2860b7ea3a1d60213ee7228bd274bc4f8b170772.tar.xz | |
Fold predicable instructions into MOVCC / t2MOVCC.
The ARM select instructions are just predicated moves. If the select is
the only use of an operand, the instruction defining the operand can be
predicated instead, saving one instruction and decreasing register
pressure.
This implementation can turn AND/ORR/EOR instructions into their
corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to
predicate any instruction, but we don't yet support predicated
instructions in SSA form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161994 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 76c897c795..9da8f1c3e3 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3939,7 +3939,7 @@ def BCCZi64 : PseudoInst<(outs), // a two-value operand where a dag node expects two operands. :( let neverHasSideEffects = 1 in { -let isCommutable = 1 in +let isCommutable = 1, usesCustomInserter = 1 in def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p), 4, IIC_iCMOVr, [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>, |