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ARM
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ARMInstrInfo.td
Commit message (
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Author
Age
*
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instruction...
Mihai Popa
2013-05-13
*
s tightens up the encoding description for ARM post-indexed ldr instructions....
Mihai Popa
2013-04-30
*
ARM: Fix encoding of hint instruction for Thumb.
Quentin Colombet
2013-04-26
*
Fix treatment of ARM unallocated hint instructions.
Quentin Colombet
2013-04-17
*
ARM: Correct printing of pre-indexed operands.
Quentin Colombet
2013-04-12
*
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.
Tim Northover
2013-04-10
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ARM scheduler model: Add scheduler info to more instructions and resource
Arnold Schwaighofer
2013-04-05
*
ARM Scheduler Model: Add resources instructions, map resources in subtargets
Arnold Schwaighofer
2013-04-01
*
Revert ARM Scheduler Model: Add resources instructions, map resources
Arnold Schwaighofer
2013-03-26
*
ARM Scheduler Model: Add resources instructions, map resources in subtargets
Arnold Schwaighofer
2013-03-26
*
ARM: Convenience aliases for 'srs*' instructions.
Jim Grosbach
2013-02-23
*
Move MRI liveouts to ARM return instructions.
Jakob Stoklund Olesen
2013-02-05
*
Add a special ARM trap encoding for NaCl.
Eli Bendersky
2013-01-30
*
Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.
Silviu Baranga
2012-11-29
*
Remove hard coded registers in ARM ldrexd and strexd instructions
Weiming Zhao
2012-11-16
*
Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all
Chad Rosier
2012-11-06
*
Fix a miscompilation caused by a typo. When turning a adde with negative value
Evan Cheng
2012-10-24
*
Add LLVM support for Swift.
Bob Wilson
2012-09-29
*
MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648
Evan Cheng
2012-09-18
*
Remove predicated pseudo-instructions.
Jakob Stoklund Olesen
2012-09-05
*
Patch to implement UMLAL/SMLAL instructions for the ARM architecture
Arnold Schwaighofer
2012-09-04
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Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ...
Jakob Stoklund Olesen
2012-08-28
*
Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
Jakob Stoklund Olesen
2012-08-27
*
Explicitly mark LEApcrel pseudos with hasSideEffects.
Jakob Stoklund Olesen
2012-08-24
*
Add missing SDNPSideEffect flags.
Jakob Stoklund Olesen
2012-08-24
*
Fix undefined behavior (negation of INT_MIN) in ARM backend.
Richard Smith
2012-08-24
*
Add ADD and SUB to the predicable ARM instructions.
Jakob Stoklund Olesen
2012-08-16
*
Handle ARM MOVCC optimization in PeepholeOptimizer.
Jakob Stoklund Olesen
2012-08-16
*
Fold predicable instructions into MOVCC / t2MOVCC.
Jakob Stoklund Olesen
2012-08-15
*
Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows una...
Evan Cheng
2012-08-15
*
Add missing Rfalse operand to the predicated pseudo-instructions.
Jakob Stoklund Olesen
2012-08-15
*
Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM
Arnold Schwaighofer
2012-08-12
*
Patch to implement UMLAL/SMLAL instructions for the ARM architecture
Arnold Schwaighofer
2012-08-09
*
ARM: Tidy up. Remove unused template parameters.
Jim Grosbach
2012-08-02
*
Fix #13241, a bug around shift immediate operand for ARM instruction ADR.
Jiangning Liu
2012-08-02
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ARM: Remove redundant instalias.
Jim Grosbach
2012-08-01
*
Clean up formatting.
Jim Grosbach
2012-08-01
*
Remove variable_ops from ARM call instructions.
Jakob Stoklund Olesen
2012-07-13
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(sub X, imm) gets canonicalized to (add X, -imm)
Evan Cheng
2012-06-23
*
ARM: Add a better diagnostic for some out of range immediates.
Jim Grosbach
2012-06-22
*
Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from a
Lang Hames
2012-06-22
*
Add DAG-combines for aggressive FMA formation.
Lang Hames
2012-06-19
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ARM: Define generic HINT instruction.
Jim Grosbach
2012-06-18
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Re-enable the CMN instruction.
Bill Wendling
2012-06-11
*
Fix typos found by http://github.com/lyda/misspell-check
Benjamin Kramer
2012-06-02
*
ARM: properly handle alignment for struct byval.
Manman Ren
2012-06-01
*
ARM: support struct byval in llvm
Manman Ren
2012-06-01
*
Remove incorrect pattern for ARM SMML instruction.
Tim Northover
2012-05-17
*
Added the missing bit definition for the 4th bit of the STR (post reg) instru...
Silviu Baranga
2012-05-11
*
ARM: improved assembler diagnostics for missing CPU features.
Jim Grosbach
2012-04-24
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