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author | Lang Hames <lhames@gmail.com> | 2012-06-19 22:51:23 +0000 |
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committer | Lang Hames <lhames@gmail.com> | 2012-06-19 22:51:23 +0000 |
commit | d693cafcfb9e67ba7040cb810e4409a166421482 (patch) | |
tree | 86a20682e48b7aaf402fc95f6497eae48e8fa89a /lib/Target/ARM/ARMInstrInfo.td | |
parent | fa8becb6f9e8aa2cbe3bab79e1fc4cdf2ffbb8e5 (diff) | |
download | llvm-d693cafcfb9e67ba7040cb810e4409a166421482.tar.gz llvm-d693cafcfb9e67ba7040cb810e4409a166421482.tar.bz2 llvm-d693cafcfb9e67ba7040cb810e4409a166421482.tar.xz |
Add DAG-combines for aggressive FMA formation.
This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or
FSUB + FMUL. The combines are performed when:
(a) Either
AllowExcessFPPrecision option (-enable-excess-fp-precision for llc)
OR
UnsafeFPMath option (-enable-unsafe-fp-math)
are set, and
(b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of
the FADD/FSUB, and
(c) The FMUL only has one user (the FADD/FSUB).
If your target has fast FMA instructions you can make use of these combines by
overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for
types supported by your FMA instruction, and adding patterns to match ISD::FMA
to your FMA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158757 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrInfo.td')
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 5131152d1e..81e3527a6f 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -236,7 +236,7 @@ def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">; // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. // But only select them if more precision in FP computation is allowed. // Do not use them for Darwin platforms. -def UseFusedMAC : Predicate<"!TM.Options.NoExcessFPPrecision && " +def UseFusedMAC : Predicate<"TM.Options.AllowExcessFPPrecision && " "!Subtarget->isTargetDarwin()">; def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || " "Subtarget->isTargetDarwin()">; |