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| author | Jim Grosbach <grosbach@apple.com> | 2011-06-30 23:38:17 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-06-30 23:38:17 +0000 |
| commit | 2a7b41ba4d3eb3c6003f6768dc20b28d83eac265 (patch) | |
| tree | 74d0d6ab330b8b4317e30390e0145a8b6bfe934e /lib/Target/ARM/ARMInstrThumb.td | |
| parent | 73744df0c467895bac9e25d5c62f34a0a8fcc4f9 (diff) | |
| download | llvm-2a7b41ba4d3eb3c6003f6768dc20b28d83eac265.tar.gz llvm-2a7b41ba4d3eb3c6003f6768dc20b28d83eac265.tar.bz2 llvm-2a7b41ba4d3eb3c6003f6768dc20b28d83eac265.tar.xz | |
Refact ARM Thumb1 tMOVr instruction family.
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrThumb.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 42 |
1 files changed, 4 insertions, 38 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index b2bf344e42..0b14976b7f 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -1054,15 +1054,15 @@ def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, // TODO: A7-73: MOV(2) - mov setting flag. let neverHasSideEffects = 1 in { -def tMOVr : Thumb1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), AddrModeNone, +def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>, - T1Special<0b1000> { + T1Special<{1,0,?,?}> { // A8.6.97 bits<4> Rd; bits<4> Rm; - // Bits {7-6} are encoded by the T1Special value. - let Inst{5-3} = Rm{2-0}; + let Inst{7} = Rd{3}; + let Inst{6-3} = Rm; let Inst{2-0} = Rd{2-0}; } let Defs = [CPSR] in @@ -1075,40 +1075,6 @@ def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, let Inst{5-3} = Rm; let Inst{2-0} = Rd; } - -// FIXME: Do we really need separate instructions for GPR<-->tGPR like this? -// They all map to the same instruction (MOV encoding T1). -def tMOVgpr2tgpr : Thumb1pI<(outs tGPR:$Rd), (ins GPR:$Rm), AddrModeNone, - Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>, - T1Special<{1,0,0,?}> { - // A8.6.97 - bits<4> Rd; - bits<4> Rm; - // Bit {7} is encoded by the T1Special value. - let Inst{6-3} = Rm; - let Inst{2-0} = Rd{2-0}; -} -def tMOVtgpr2gpr : Thumb1pI<(outs GPR:$Rd), (ins tGPR:$Rm), AddrModeNone, - Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>, - T1Special<{1,0,?,0}> { - // A8.6.97 - bits<4> Rd; - bits<4> Rm; - // Bit {6} is encoded by the T1Special value. - let Inst{7} = Rd{3}; - let Inst{5-3} = Rm{2-0}; - let Inst{2-0} = Rd{2-0}; -} -def tMOVgpr2gpr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, - Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>, - T1Special<{1,0,?,?}> { - // A8.6.97 - bits<4> Rd; - bits<4> Rm; - let Inst{7} = Rd{3}; - let Inst{6-3} = Rm; - let Inst{2-0} = Rd{2-0}; -} } // neverHasSideEffects // Multiply register |