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| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-04-25 17:24:24 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2014-04-25 17:24:24 +0000 |
| commit | 04f826c0625a9701dd941fa0fb5db110f5971421 (patch) | |
| tree | 7f6d74740698735b3405af5ad6d413953f041176 /lib/Target/ARM/ARMInstrThumb2.td | |
| parent | 5d71d87bff0c22dd117e378d1e6289f72d675baf (diff) | |
| download | llvm-04f826c0625a9701dd941fa0fb5db110f5971421.tar.gz llvm-04f826c0625a9701dd941fa0fb5db110f5971421.tar.bz2 llvm-04f826c0625a9701dd941fa0fb5db110f5971421.tar.xz | |
ARM: provide a new generic hint intrinsic
Introduce the llvm.arm.hint(i32) intrinsic that can be used to inject hints into
the instruction stream. This is particularly useful for generating IR from a
compiler where the user may inject an intrinsic (e.g. __yield). These are then
pattern substituted into the correct instruction which already existed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207242 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrThumb2.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index c30bf69762..1e4aa0d6ab 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3671,7 +3671,8 @@ def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>; // A6.3.4 Branches and miscellaneous control // Table A6-14 Change Processor State, and hint instructions -def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",[]> { +def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm", + [(int_arm_hint imm0_239:$imm)]> { bits<8> imm; let Inst{31-3} = 0b11110011101011111000000000000; let Inst{7-0} = imm; |