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| author | Richard Barton <richard.barton@arm.com> | 2012-07-10 12:51:09 +0000 |
|---|---|---|
| committer | Richard Barton <richard.barton@arm.com> | 2012-07-10 12:51:09 +0000 |
| commit | fae96f17b4b022fccd94a143698112a17d8ddf05 (patch) | |
| tree | 2e3dd08f996768f671cc1e8600a617e43b112c48 /lib/Target/ARM/ARMInstrVFP.td | |
| parent | 97a0c6bc91bf31fa701dda478d9616c2de6b2393 (diff) | |
| download | llvm-fae96f17b4b022fccd94a143698112a17d8ddf05.tar.gz llvm-fae96f17b4b022fccd94a143698112a17d8ddf05.tar.bz2 llvm-fae96f17b4b022fccd94a143698112a17d8ddf05.tar.xz | |
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrVFP.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrVFP.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 4e2cda433b..23c132e4f6 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -567,8 +567,8 @@ def VMOVRRS : AVConv3I<0b11000101, 0b1010, bits<4> Rt2; // Encode instruction operands. - let Inst{3-0} = src1{3-0}; - let Inst{5} = src1{4}; + let Inst{3-0} = src1{4-1}; + let Inst{5} = src1{0}; let Inst{15-12} = Rt; let Inst{19-16} = Rt2; @@ -617,8 +617,8 @@ def VMOVSRR : AVConv5I<0b11000100, 0b1010, bits<4> src2; // Encode instruction operands. - let Inst{3-0} = dst1{3-0}; - let Inst{5} = dst1{4}; + let Inst{3-0} = dst1{4-1}; + let Inst{5} = dst1{0}; let Inst{15-12} = src1; let Inst{19-16} = src2; |