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| author | Dan Gohman <gohman@apple.com> | 2008-10-03 15:45:36 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-10-03 15:45:36 +0000 |
| commit | d735b8019b0f297d7c14b55adcd887af24d8e602 (patch) | |
| tree | 9019ef6d07a30709c5afbe52903a7cdfd9615cb1 /lib/Target/ARM/ARMRegisterInfo.cpp | |
| parent | 06a62886fbca6214945958e28b16a82b470f6b2e (diff) | |
| download | llvm-d735b8019b0f297d7c14b55adcd887af24d8e602.tar.gz llvm-d735b8019b0f297d7c14b55adcd887af24d8e602.tar.bz2 llvm-d735b8019b0f297d7c14b55adcd887af24d8e602.tar.xz | |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 3a0a57d92d..2091899f00 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -540,7 +540,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); bool isThumb = AFI->isThumbFunction(); - while (!MI.getOperand(i).isFrameIndex()) { + while (!MI.getOperand(i).isFI()) { ++i; assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); } @@ -1020,7 +1020,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) { for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) - if (I->getOperand(i).isFrameIndex()) { + if (I->getOperand(i).isFI()) { unsigned Opcode = I->getOpcode(); const TargetInstrDesc &Desc = TII.get(Opcode); unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); @@ -1086,7 +1086,7 @@ static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, int Opc, unsigned Area, const ARMSubtarget &STI) { while (MBBI != MBB.end() && - MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFrameIndex()) { + MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) { if (Area != 0) { bool Done = false; unsigned Category = 0; @@ -1250,7 +1250,7 @@ static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { return ((MI->getOpcode() == ARM::FLDD || MI->getOpcode() == ARM::LDR || MI->getOpcode() == ARM::tRestore) && - MI->getOperand(1).isFrameIndex() && + MI->getOperand(1).isFI() && isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); } |