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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-03-06 18:44:11 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-03-06 18:44:11 +0000
commit14f87e01ca704b2916a4c0c5360f3d703c85806f (patch)
treef60b4e032fc097ab82ca82d608f9cfe65a3bf0f8 /lib/Target/ARM/ARMRegisterInfo.td
parent158c8a49c23d01297e7913c03c1fdb0760aee3a8 (diff)
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Allow the same types in DPair as in QPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152129 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.td')
-rw-r--r--lib/Target/ARM/ARMRegisterInfo.td3
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index bbd8c92720..527e8b5a6a 100644
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -309,7 +309,8 @@ def TuplesOE2D : RegisterTuples<[dsub_0, dsub_1],
// Register class representing a pair of consecutive D registers.
// Use the Q registers for the even-odd pairs.
-def DPair : RegisterClass<"ARM", [v2i64], 128, (interleave QPR, TuplesOE2D)> {
+def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+ 128, (interleave QPR, TuplesOE2D)> {
// Allocate starting at non-VFP2 registers D16-D31 first.
let AltOrders = [(rotl DPair, 16)];
let AltOrderSelect = [{ return 1; }];