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| author | Owen Anderson <resistor@mac.com> | 2011-08-09 22:48:45 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-09 22:48:45 +0000 |
| commit | 51c9805c4bcca635bc6a854e4a246ebd4258f512 (patch) | |
| tree | 55ded190997f1ab6fc7be202c28c2b5ba8c444c2 /lib/Target/ARM/ARMRegisterInfo.td | |
| parent | 18deb04e9c4285719972d10e92605e28f074614c (diff) | |
| download | llvm-51c9805c4bcca635bc6a854e4a246ebd4258f512.tar.gz llvm-51c9805c4bcca635bc6a854e4a246ebd4258f512.tar.bz2 llvm-51c9805c4bcca635bc6a854e4a246ebd4258f512.tar.xz | |
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137168 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.td')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 98357d48f3..cf3d66873b 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -215,6 +215,16 @@ def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), }]; } +// GPRs without the PC. Some ARM instructions do not allow the PC in +// certain operand slots, particularly as the destination. Primarily +// useful for disassembly. +def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { + let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; + let AltOrderSelect = [{ + return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); + }]; +} + // restricted GPR register class. Many Thumb2 instructions allow the full // register range for operands, but have undefined behaviours when PC // or SP (R13 or R15) are used. The ARM ISA refers to these operands |