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| author | Alp Toker <alp@nuanti.com> | 2014-01-24 17:20:08 +0000 |
|---|---|---|
| committer | Alp Toker <alp@nuanti.com> | 2014-01-24 17:20:08 +0000 |
| commit | ae43cab6bab0e5bcdbe2971bf718712559625e39 (patch) | |
| tree | 536b346c514acfc8d7f3c2e424e1295de63e516a /lib/Target/ARM/ARMRegisterInfo.td | |
| parent | 27ce8feb4adbb13c0efcc2d560c93dfb71785cb2 (diff) | |
| download | llvm-ae43cab6bab0e5bcdbe2971bf718712559625e39.tar.gz llvm-ae43cab6bab0e5bcdbe2971bf718712559625e39.tar.bz2 llvm-ae43cab6bab0e5bcdbe2971bf718712559625e39.tar.xz | |
Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.td')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index d0457618ef..7f0fe05738 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -214,7 +214,7 @@ def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { } // GPRs without the PC but with APSR. Some instructions allow accessing the -// APSR, while actually encoding PC in the register field. This is usefull +// APSR, while actually encoding PC in the register field. This is useful // for assembly and disassembly only. def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> { let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)]; |