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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-04-05 04:42:00 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-04-05 04:42:00 +0000 |
| commit | 08da4865576056f997a9c8013240d716018f7edf (patch) | |
| tree | f99588a26e23f5554daa91c4393b8088eb19f222 /lib/Target/ARM/ARMSchedule.td | |
| parent | d4d7613af3fa3ba9abd7ea0828d9dadc23dd73ea (diff) | |
| download | llvm-08da4865576056f997a9c8013240d716018f7edf.tar.gz llvm-08da4865576056f997a9c8013240d716018f7edf.tar.bz2 llvm-08da4865576056f997a9c8013240d716018f7edf.tar.xz | |
ARM scheduler model: Swift has varying latencies, uops for simple ALU ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178842 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSchedule.td')
| -rw-r--r-- | lib/Target/ARM/ARMSchedule.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index 7eb5ff665a..136a90aa95 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -71,6 +71,8 @@ def : PredicateProlog<[{ (void)TII; }]>; +def IsPredicatedPred : SchedPredicate<[{TII->isPredicated(MI)}]>; + //===----------------------------------------------------------------------===// // Instruction Itinerary classes used for ARM // |