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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-04 22:15:46 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-04 22:15:46 +0000 |
| commit | 611c6e135910779a8d1ed6db023d87f19799f6ac (patch) | |
| tree | 71d1b3212d87e93502476173767bb85cce64cc13 /lib/Target/ARM/ARMSchedule.td | |
| parent | ede7eeae328d455b00d600639adacda695a499b6 (diff) | |
| download | llvm-611c6e135910779a8d1ed6db023d87f19799f6ac.tar.gz llvm-611c6e135910779a8d1ed6db023d87f19799f6ac.tar.bz2 llvm-611c6e135910779a8d1ed6db023d87f19799f6ac.tar.xz | |
ARM sched model: Add divsion, loads, branches, vfp cvt
Add some generic SchedWrites and assign resources for Swift and Cortex A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183257 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSchedule.td')
| -rw-r--r-- | lib/Target/ARM/ARMSchedule.td | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index 2d088de96e..f25e9c2e2a 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -69,6 +69,21 @@ def WriteCMP : SchedWrite; def WriteCMPsi : SchedWrite; def WriteCMPsr : SchedWrite; +// Division. +def WriteDiv : SchedWrite; + +// Loads. +def WriteLd : SchedWrite; +def WritePreLd : SchedWrite; + +// Branches. +def WriteBr : SchedWrite; +def WriteBrL : SchedWrite; +def WriteBrTbl : SchedWrite; + +// Fixpoint conversions. +def WriteCvtFP : SchedWrite; + // Define TII for use in SchedVariant Predicates. def : PredicateProlog<[{ const ARMBaseInstrInfo *TII = |