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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-18 20:31:01 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-18 20:31:01 +0000 |
| commit | 928eb49cae286c95dceecf4442997dd561c6e3b7 (patch) | |
| tree | d65ac9dd3b6f18abc632f4d186d430e075ded25a /lib/Target/ARM/ARMSchedule.td | |
| parent | d65077a50901cbe55d8285bb1149eb8ba8210a58 (diff) | |
| download | llvm-928eb49cae286c95dceecf4442997dd561c6e3b7.tar.gz llvm-928eb49cae286c95dceecf4442997dd561c6e3b7.tar.bz2 llvm-928eb49cae286c95dceecf4442997dd561c6e3b7.tar.xz | |
Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSchedule.td')
| -rw-r--r-- | lib/Target/ARM/ARMSchedule.td | 16 |
1 files changed, 1 insertions, 15 deletions
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index 1c96976d6c..b60ccca468 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -8,19 +8,6 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// Functional units across ARM processors -// -def FU_Issue : FuncUnit; // issue -def FU_Pipe0 : FuncUnit; // pipeline 0 -def FU_Pipe1 : FuncUnit; // pipeline 1 -def FU_LdSt0 : FuncUnit; // pipeline 0 load/store -def FU_LdSt1 : FuncUnit; // pipeline 1 load/store -def FU_NPipe : FuncUnit; // NEON ALU/MUL pipe -def FU_NLSPipe : FuncUnit; // NEON LS pipe -def FU_DRegsVFP: FuncUnit; // FP register set, VFP side -def FU_DRegsN : FuncUnit; // FP register set, NEON side - -//===----------------------------------------------------------------------===// // Instruction Itinerary classes used for ARM // def IIC_iALUx : InstrItinClass; @@ -165,8 +152,7 @@ def IIC_VTBX4 : InstrItinClass; //===----------------------------------------------------------------------===// // Processor instruction itineraries. -def GenericItineraries : ProcessorItineraries<[]>; - +def GenericItineraries : ProcessorItineraries<[], []>; include "ARMScheduleV6.td" include "ARMScheduleA8.td" |