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| author | Andrew Trick <atrick@apple.com> | 2012-06-29 07:10:41 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-06-29 07:10:41 +0000 |
| commit | 3e4b3b9043b1ced24e07d8d1174feeee06c6912e (patch) | |
| tree | f31c2d3c63fc1da8b3b598c433759ae8391e62ed /lib/Target/ARM/ARMScheduleA8.td | |
| parent | 94e3b388e561ce980c861e092bf378bf40202268 (diff) | |
| download | llvm-3e4b3b9043b1ced24e07d8d1174feeee06c6912e.tar.gz llvm-3e4b3b9043b1ced24e07d8d1174feeee06c6912e.tar.bz2 llvm-3e4b3b9043b1ced24e07d8d1174feeee06c6912e.tar.xz | |
Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."
This reverts commit r159406. I noticed a performance regression so I'll back out for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA8.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 34 |
1 files changed, 14 insertions, 20 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index 61de00a208..eb1083ca23 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -155,30 +155,28 @@ def CortexA8Itineraries : MultiIssueItineraries< // Load multiple, def is the 5th operand. Pipeline 0 only. // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. InstrItinData<IIC_iLoad_m , [InstrStage<2, [A8_Pipe0], 0>, - InstrStage<2, [A8_LSPipe]>], - [1, 1, 1, 1, 3], [], -1>, // dynamic uops + InstrStage<2, [A8_LSPipe]>], [1, 1, 1, 1, 3]>, // // Load multiple + update, defs are the 1st and 5th operands. InstrItinData<IIC_iLoad_mu , [InstrStage<3, [A8_Pipe0], 0>, - InstrStage<3, [A8_LSPipe]>], - [2, 1, 1, 1, 3], [], -1>, // dynamic uops + InstrStage<3, [A8_LSPipe]>], [2, 1, 1, 1, 3]>, // // Load multiple plus branch InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [A8_Pipe0], 0>, InstrStage<3, [A8_LSPipe]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>], - [1, 2, 1, 1, 3], [], -1>, // dynamic uops + [1, 2, 1, 1, 3]>, // // Pop, def is the 3rd operand. InstrItinData<IIC_iPop , [InstrStage<3, [A8_Pipe0], 0>, - InstrStage<3, [A8_LSPipe]>], - [1, 1, 3], [], -1>, // dynamic uops + InstrStage<3, [A8_LSPipe]>], [1, 1, 3]>, // // Push, def is the 3th operand. InstrItinData<IIC_iPop_Br, [InstrStage<3, [A8_Pipe0], 0>, InstrStage<3, [A8_LSPipe]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>], - [1, 1, 3], [], -1>, // dynamic uops + [1, 1, 3]>, + // // iLoadi + iALUr for t2LDRpci_pic. InstrItinData<IIC_iLoadiALU, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, @@ -233,13 +231,12 @@ def CortexA8Itineraries : MultiIssueItineraries< // Store multiple. Pipeline 0 only. // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers. InstrItinData<IIC_iStore_m , [InstrStage<2, [A8_Pipe0], 0>, - InstrStage<2, [A8_LSPipe]>], - [], [], -1>, // dynamic uops + InstrStage<2, [A8_LSPipe]>]>, // // Store multiple + update InstrItinData<IIC_iStore_mu, [InstrStage<2, [A8_Pipe0], 0>, - InstrStage<2, [A8_LSPipe]>], - [2], [], -1>, // dynamic uops + InstrStage<2, [A8_LSPipe]>], [2]>, + // // Preload InstrItinData<IIC_Preload, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, @@ -400,16 +397,14 @@ def CortexA8Itineraries : MultiIssueItineraries< InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, InstrStage<1, [A8_NLSPipe], 0>, - InstrStage<1, [A8_LSPipe]>], - [1, 1, 1, 2], [], -1>, // dynamic uops + InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 2]>, // // FP Load Multiple + update InstrItinData<IIC_fpLoad_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, InstrStage<1, [A8_NLSPipe], 0>, - InstrStage<1, [A8_LSPipe]>], - [2, 1, 1, 1, 2], [], -1>, // dynamic uops + InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 2]>, // // Single-precision FP Store InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, @@ -428,16 +423,15 @@ def CortexA8Itineraries : MultiIssueItineraries< InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, InstrStage<1, [A8_NLSPipe], 0>, - InstrStage<1, [A8_LSPipe]>], - [1, 1, 1, 1], [], -1>, // dynamic uops + InstrStage<1, [A8_LSPipe]>], [1, 1, 1, 1]>, // // FP Store Multiple + update InstrItinData<IIC_fpStore_mu,[InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>, InstrStage<1, [A8_NLSPipe], 0>, InstrStage<1, [A8_LSPipe]>, InstrStage<1, [A8_NLSPipe], 0>, - InstrStage<1, [A8_LSPipe]>], - [2, 1, 1, 1, 1], [], -1>, // dynamic uops + InstrStage<1, [A8_LSPipe]>], [2, 1, 1, 1, 1]>, + // NEON // Issue through integer pipeline, and execute in NEON unit. // |