diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-07 01:50:48 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-07 01:50:48 +0000 |
| commit | 5a50ceeaea980962c1982ad535226c7ab06c971c (patch) | |
| tree | 4a833b2b855be5707dd7c13552403bae9cae448a /lib/Target/ARM/ARMScheduleA8.td | |
| parent | b046810fe4a00a12518ba3020b697929c51eb58e (diff) | |
| download | llvm-5a50ceeaea980962c1982ad535226c7ab06c971c.tar.gz llvm-5a50ceeaea980962c1982ad535226c7ab06c971c.tar.bz2 llvm-5a50ceeaea980962c1982ad535226c7ab06c971c.tar.xz | |
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115898 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA8.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA8.td | 36 |
1 files changed, 20 insertions, 16 deletions
diff --git a/lib/Target/ARM/ARMScheduleA8.td b/lib/Target/ARM/ARMScheduleA8.td index 714bf2e635..ac4da75e96 100644 --- a/lib/Target/ARM/ARMScheduleA8.td +++ b/lib/Target/ARM/ARMScheduleA8.td @@ -414,54 +414,58 @@ def CortexA8Itineraries : ProcessorItineraries< InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>], + InstrStage<2, [A8_NLSPipe]>], [2, 1]>, // // Double-precision FP Load // use A8_Issue to enforce the 1 load/store per cycle limit InstrItinData<IIC_fpLoad64, [InstrStage<2, [A8_Issue], 0>, - InstrStage<1, [A8_Pipe0], 0>, - InstrStage<1, [A8_Pipe1]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>], + InstrStage<2, [A8_NLSPipe]>], [2, 1]>, // // FP Load Multiple // use A8_Issue to enforce the 1 load/store per cycle limit - InstrItinData<IIC_fpLoadm, [InstrStage<3, [A8_Issue], 0>, - InstrStage<2, [A8_Pipe0], 0>, - InstrStage<2, [A8_Pipe1]>, + InstrItinData<IIC_fpLoad_m, [InstrStage<3, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], [1, 1, 1, 2]>, + // + // FP Load Multiple + update + InstrItinData<IIC_fpLoad_mu,[InstrStage<3, [A8_Issue], 0>, + InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<1, [A8_LdSt0], 0>, + InstrStage<1, [A8_NLSPipe]>], [2, 1, 1, 1, 2]>, // // Single-precision FP Store // use A8_Issue to enforce the 1 load/store per cycle limit InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>], + InstrStage<2, [A8_NLSPipe]>], [1, 1]>, // // Double-precision FP Store // use A8_Issue to enforce the 1 load/store per cycle limit InstrItinData<IIC_fpStore64,[InstrStage<2, [A8_Issue], 0>, - InstrStage<1, [A8_Pipe0], 0>, - InstrStage<1, [A8_Pipe1]>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>], + InstrStage<2, [A8_NLSPipe]>], [1, 1]>, // // FP Store Multiple // use A8_Issue to enforce the 1 load/store per cycle limit - InstrItinData<IIC_fpStorem, [InstrStage<3, [A8_Issue], 0>, - InstrStage<2, [A8_Pipe0], 0>, - InstrStage<2, [A8_Pipe1]>, + InstrItinData<IIC_fpStore_m,[InstrStage<3, [A8_Issue], 0>, InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0], 0>, - InstrStage<1, [A8_NLSPipe]>]>, + InstrStage<1, [A8_NLSPipe]>], [1, 1, 1, 1]>, + // + // FP Store Multiple + update + InstrItinData<IIC_fpStore_mu,[InstrStage<3, [A8_Issue], 0>, + InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<1, [A8_LdSt0], 0>, + InstrStage<1, [A8_NLSPipe]>], [2, 1, 1, 1, 1]>, // NEON // Issue through integer pipeline, and execute in NEON unit. |