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author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-07 01:10:36 +0000 |
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committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-07 01:10:36 +0000 |
commit | 873ff29514f13f6919f172ba430994ff99becbd2 (patch) | |
tree | 998bba5137d9f24b1ce0cba2b95d6cab74d7baa5 /lib/Target/ARM/ARMScheduleSwift.td | |
parent | 0efc78257b56d2ba45127e1a3f18b524a1c3dd57 (diff) | |
download | llvm-873ff29514f13f6919f172ba430994ff99becbd2.tar.gz llvm-873ff29514f13f6919f172ba430994ff99becbd2.tar.bz2 llvm-873ff29514f13f6919f172ba430994ff99becbd2.tar.xz |
ARM sched model: Add VFP div instruction on Swift
Reapply 183271.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183472 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleSwift.td')
-rw-r--r-- | lib/Target/ARM/ARMScheduleSwift.td | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td index 1c9058c250..f29efb8cb8 100644 --- a/lib/Target/ARM/ARMScheduleSwift.td +++ b/lib/Target/ARM/ARMScheduleSwift.td @@ -2043,6 +2043,22 @@ let SchedModel = SwiftModel in { (instregex "VST4LN(d|q)(8|16|32)_UPD", "VST4LN(d|q)(8|16|32)Pseudo_UPD")>; + // 4.2.44 VFP, Divide and Square Root + def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { + let NumMicroOps = 1; + let Latency = 17; + let ResourceCycles = [1, 15]; + } + def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> { + let NumMicroOps = 1; + let Latency = 32; + let ResourceCycles = [1, 30]; + } + def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>; + def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>; + + // Not specified. + def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>; // Preload. def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0; let ResourceCycles = [0]; |