diff options
| author | Alp Toker <alp@nuanti.com> | 2014-01-24 17:20:08 +0000 |
|---|---|---|
| committer | Alp Toker <alp@nuanti.com> | 2014-01-24 17:20:08 +0000 |
| commit | ae43cab6bab0e5bcdbe2971bf718712559625e39 (patch) | |
| tree | 536b346c514acfc8d7f3c2e424e1295de63e516a /lib/Target/ARM/ARMScheduleSwift.td | |
| parent | 27ce8feb4adbb13c0efcc2d560c93dfb71785cb2 (diff) | |
| download | llvm-ae43cab6bab0e5bcdbe2971bf718712559625e39.tar.gz llvm-ae43cab6bab0e5bcdbe2971bf718712559625e39.tar.bz2 llvm-ae43cab6bab0e5bcdbe2971bf718712559625e39.tar.xz | |
Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleSwift.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleSwift.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td index 8d7dbc2460..b03d5ff44c 100644 --- a/lib/Target/ARM/ARMScheduleSwift.td +++ b/lib/Target/ARM/ARMScheduleSwift.td @@ -1721,7 +1721,7 @@ let SchedModel = SwiftModel in { SchedVar<SwiftLMAddr3Pred, [SwiftWriteLM9Cy, SwiftWriteLM10Cy, SwiftWriteLM13CyNo, SwiftWriteP01OneCycle, SwiftVLDMPerm3]>, - // Load of a Q register (not neccessarily true). We should not be mapping to + // Load of a Q register (not necessarily true). We should not be mapping to // 4 S registers, either. SchedVar<SwiftLMAddr4Pred, [SwiftWriteLM4Cy, SwiftWriteLM4CyNo, SwiftWriteLM4CyNo, SwiftWriteLM4CyNo]>, @@ -1858,7 +1858,7 @@ let SchedModel = SwiftModel in { // Assume 5 D registers. SchedVar<SwiftLMAddr10Pred, [SwiftWriteSTM6]>, SchedVar<SwiftLMAddr11Pred, [SwiftWriteSTM12]>, - // Asume three Q registers. + // Assume three Q registers. SchedVar<SwiftLMAddr12Pred, [SwiftWriteSTM4]>, SchedVar<SwiftLMAddr13Pred, [SwiftWriteSTM14]>, // Assume 7 D registers. |