ARM scheduler model: Add scheduler info to more instructions and resource

descriptions for compares

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178844 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 9 insertions, 5 deletions

diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td
index 4a87faaac0..7c6df41070 100644
--- a/lib/Target/ARM/ARMScheduleSwift.td
+++ b/lib/Target/ARM/ARMScheduleSwift.td
@@ -1113,23 +1113,22 @@ let SchedModel = SwiftModel in {
   def SwiftWriteALUsi : SchedWriteVariant<[
     // lsl #2, lsl #1, or lsr #1.
     SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01TwoCycle]>,
-    // Arbitrary imm shift.
     SchedVar<NoSchedPred,             [WriteALU]>
   ]>;
   def SwiftWriteALUsr : SchedWriteVariant<[
     SchedVar<IsPredicatedPred, [SwiftWriteP01ThreeCycleTwoUops]>,
-    SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]>
+    SchedVar<NoSchedPred,      [SwiftWriteP01TwoCycle]>
   ]>;
   def SwiftWriteALUSsr : SchedWriteVariant<[
     SchedVar<IsPredicatedPred, [SwiftWriteP0ThreeCycleThreeUops]>,
-    SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]>
+    SchedVar<NoSchedPred,      [SwiftWriteP01TwoCycle]>
   ]>;
   def SwiftReadAdvanceALUsr : SchedReadVariant<[
     SchedVar<IsPredicatedPred, [SchedReadAdvance<2>]>,
-    SchedVar<NoSchedPred, [NoReadAdvance]>
+    SchedVar<NoSchedPred,      [NoReadAdvance]>
   ]>;
   // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
-  // AND,BIC, EOR,ORN,ORR
+  // AND,BIC,EOR,ORN,ORR
   // CLZ,RBIT,REV,REV16,REVSH,PKH
   def : WriteRes<WriteALU, [SwiftUnitP01]>;
   def : SchedAlias<WriteALUsi, SwiftWriteALUsi>;
@@ -1137,4 +1136,9 @@ let SchedModel = SwiftModel in {
   def : SchedAlias<WriteALUSsr, SwiftWriteALUSsr>;
   def : ReadAdvance<ReadALU, 0>;
   def : SchedAlias<ReadALUsr, SwiftReadAdvanceALUsr>;
+
+  // 4.2.5 Integer comparison
+  def : WriteRes<WriteCMP, [SwiftUnitP01]>;
+  def : WriteRes<WriteCMPsi, [SwiftUnitP01]>;
+  def : WriteRes<WriteCMPsr, [SwiftUnitP01]>;
 }