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| author | Evan Cheng <evan.cheng@apple.com> | 2010-09-09 18:18:55 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-09-09 18:18:55 +0000 |
| commit | 5f54ce347368105260be2cec497b6a4199dc5789 (patch) | |
| tree | dc2bae4e74d050c15882a22255e3a65453003c7a /lib/Target/ARM/ARMScheduleV6.td | |
| parent | c48bf0c39451befa74b1091be2546760c72c1c91 (diff) | |
| download | llvm-5f54ce347368105260be2cec497b6a4199dc5789.tar.gz llvm-5f54ce347368105260be2cec497b6a4199dc5789.tar.bz2 llvm-5f54ce347368105260be2cec497b6a4199dc5789.tar.xz | |
For each instruction itinerary class, specify the number of micro-ops each
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleV6.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV6.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td index 08b560cc0c..b382a7a519 100644 --- a/lib/Target/ARM/ARMScheduleV6.td +++ b/lib/Target/ARM/ARMScheduleV6.td @@ -86,6 +86,11 @@ def ARMV6Itineraries : ProcessorItineraries< // Load multiple InstrItinData<IIC_iLoadm , [InstrStage<3, [V6_Pipe]>]>, + // + // Load multiple plus branch + InstrItinData<IIC_iLoadmBr , [InstrStage<3, [V6_Pipe]>, + InstrStage<1, [V6_Pipe]>]>, + // Integer store pipeline // // Immediate offset |