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author | Jim Grosbach <grosbach@apple.com> | 2014-04-03 23:43:18 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2014-04-03 23:43:18 +0000 |
commit | 81fb6bfb85d0a2789225791170beb6280769bedd (patch) | |
tree | 9a97734bc2ebfd0a08f6e1a1f45c209d174ab4d5 /lib/Target/ARM/ARMScheduleV6.td | |
parent | 6cd0131b34d570c0162388fa59741f544ccaf9e6 (diff) | |
download | llvm-81fb6bfb85d0a2789225791170beb6280769bedd.tar.gz llvm-81fb6bfb85d0a2789225791170beb6280769bedd.tar.bz2 llvm-81fb6bfb85d0a2789225791170beb6280769bedd.tar.xz |
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205583 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleV6.td')
-rw-r--r-- | lib/Target/ARM/ARMScheduleV6.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td index 0ace9bc179..57d0bfb650 100644 --- a/lib/Target/ARM/ARMScheduleV6.td +++ b/lib/Target/ARM/ARMScheduleV6.td @@ -93,7 +93,7 @@ def ARMV6Itineraries : ProcessorItineraries< InstrItinData<IIC_iMAC32 , [InstrStage<2, [V6_Pipe]>], [5, 1, 1, 2]>, InstrItinData<IIC_iMUL64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1]>, InstrItinData<IIC_iMAC64 , [InstrStage<3, [V6_Pipe]>], [6, 1, 1, 2]>, - + // Integer load pipeline // // Immediate offset @@ -181,7 +181,7 @@ def ARMV6Itineraries : ProcessorItineraries< // // Store multiple + update InstrItinData<IIC_iStore_mu , [InstrStage<3, [V6_Pipe]>], [2]>, - + // Branch // // no delay slots, so the latency of a branch is unimportant |