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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-06 06:27:31 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-06 06:27:31 +0000 |
| commit | a0792de66c8364d47b0a688c7f408efb7b10f31b (patch) | |
| tree | 74720b528520e7d3702afc6ed850dc6a6e1ce99e /lib/Target/ARM/ARMScheduleV6.td | |
| parent | 7f5124829ffcf75f598b024ec40cc83753eb72d4 (diff) | |
| download | llvm-a0792de66c8364d47b0a688c7f408efb7b10f31b.tar.gz llvm-a0792de66c8364d47b0a688c7f408efb7b10f31b.tar.bz2 llvm-a0792de66c8364d47b0a688c7f408efb7b10f31b.tar.xz | |
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleV6.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV6.td | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td index b5ae9277fc..f1dbdbc5a7 100644 --- a/lib/Target/ARM/ARMScheduleV6.td +++ b/lib/Target/ARM/ARMScheduleV6.td @@ -116,19 +116,29 @@ def ARMV6Itineraries : ProcessorItineraries< InstrItinData<IIC_iLoad_bh_siu,[InstrStage<2, [V6_Pipe]>], [5, 2, 2, 1]>, // - // Load multiple - InstrItinData<IIC_iLoadm , [InstrStage<3, [V6_Pipe]>]>, - + // Load multiple, def is the 5th operand. + InstrItinData<IIC_iLoad_m , [InstrStage<3, [V6_Pipe]>], [1, 1, 1, 1, 4]>, + // + // Load multiple + update, defs are the 1st and 5th operands. + InstrItinData<IIC_iLoad_mu , [InstrStage<3, [V6_Pipe]>], [2, 1, 1, 1, 4]>, // // Load multiple plus branch - InstrItinData<IIC_iLoadmBr , [InstrStage<3, [V6_Pipe]>, - InstrStage<1, [V6_Pipe]>]>, + InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [V6_Pipe]>, + InstrStage<1, [V6_Pipe]>], [1, 2, 1, 1, 4]>, // // iLoadi + iALUr for t2LDRpci_pic. InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>, InstrStage<1, [V6_Pipe]>], [3, 1]>, + // + // Pop, def is the 3rd operand. + InstrItinData<IIC_iPop , [InstrStage<3, [V6_Pipe]>], [1, 1, 4]>, + // + // Pop + branch, def is the 3rd operand. + InstrItinData<IIC_iPop_Br, [InstrStage<3, [V6_Pipe]>, + InstrStage<1, [V6_Pipe]>], [1, 2, 4]>, + // Integer store pipeline // // Immediate offset @@ -159,7 +169,10 @@ def ARMV6Itineraries : ProcessorItineraries< InstrItinData<IIC_iStore_bh_siu,[InstrStage<2, [V6_Pipe]>], [2, 2, 2, 1]>, // // Store multiple - InstrItinData<IIC_iStorem , [InstrStage<3, [V6_Pipe]>]>, + InstrItinData<IIC_iStore_m , [InstrStage<3, [V6_Pipe]>]>, + // + // Store multiple + update + InstrItinData<IIC_iStore_mu , [InstrStage<3, [V6_Pipe]>], [2]>, // Branch // |