diff options
| author | David Goodwin <david_goodwin@apple.com> | 2009-09-21 20:52:17 +0000 |
|---|---|---|
| committer | David Goodwin <david_goodwin@apple.com> | 2009-09-21 20:52:17 +0000 |
| commit | b2bb7db9e242c54a4a84448ab503015a148e9286 (patch) | |
| tree | ce8d32723977c655ec064bd7f3f1ae44bb6f7db0 /lib/Target/ARM/ARMScheduleV6.td | |
| parent | 28f02fdd76f4efc05d14649e0eec90ce8e71e17e (diff) | |
| download | llvm-b2bb7db9e242c54a4a84448ab503015a148e9286.tar.gz llvm-b2bb7db9e242c54a4a84448ab503015a148e9286.tar.bz2 llvm-b2bb7db9e242c54a4a84448ab503015a148e9286.tar.xz | |
Add Cortex-A8 VFP model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82483 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleV6.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV6.td | 41 |
1 files changed, 35 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td index 1cac9180df..3eadf4cc2e 100644 --- a/lib/Target/ARM/ARMScheduleV6.td +++ b/lib/Target/ARM/ARMScheduleV6.td @@ -61,10 +61,39 @@ def V6Itineraries : ProcessorItineraries<[ InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>, InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>, - InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>, - InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>, - InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>, - InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, - InstrStage<1, [FU_LdSt0]>]>, - InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]> + InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpSTAT , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpMOVSI , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpMOVDI , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpMOVIS , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpMOVID , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpUNA32 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpUNA64 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpCMP32 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpCMP64 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpCVTSD , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpCVTDS , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpCVTIS , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpCVTID , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpCVTSI , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpCVTDI , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpALU32 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpALU64 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpMUL32 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpMUL64 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpMAC32 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpMAC64 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpDIV32 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpDIV64 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpSQRT32 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpSQRT64 , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpLoad32 , [InstrStage<1, [FU_Pipe0]>, + InstrStage<1, [FU_LdSt0]>]>, + InstrItinData<IIC_fpLoad64 , [InstrStage<1, [FU_Pipe0]>, + InstrStage<1, [FU_LdSt0]>]>, + InstrItinData<IIC_fpLoadm , [InstrStage<1, [FU_Pipe0]>, + InstrStage<1, [FU_LdSt0]>]>, + InstrItinData<IIC_fpStore32, [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpStore64, [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpStorem , [InstrStage<1, [FU_Pipe0]>]> ]>; |