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author | Tim Northover <tnorthover@apple.com> | 2014-04-01 13:22:02 +0000 |
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committer | Tim Northover <tnorthover@apple.com> | 2014-04-01 13:22:02 +0000 |
commit | c077472250ef27e514f5ad44f3b258a18a70f065 (patch) | |
tree | 29202ba7c1bc69f0b720c6d9a43168d066b1aa78 /lib/Target/ARM/ARMSubtarget.h | |
parent | 279edf967edc1b2dcaaad3e263972cb4fe83b35d (diff) | |
download | llvm-c077472250ef27e514f5ad44f3b258a18a70f065.tar.gz llvm-c077472250ef27e514f5ad44f3b258a18a70f065.tar.bz2 llvm-c077472250ef27e514f5ad44f3b258a18a70f065.tar.xz |
ARM: add cyclone CPU with ZeroCycleZeroing feature.
The Cyclone CPU is similar to swift for most LLVM purposes, but does have two
preferred instructions for zeroing a VFP register. This teaches LLVM about
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205309 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSubtarget.h')
-rw-r--r-- | lib/Target/ARM/ARMSubtarget.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index 2ce99c890f..e76cc85a1a 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -177,6 +177,10 @@ protected: /// HasCRC - if true, processor supports CRC instructions bool HasCRC; + /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are + /// particularly effective at zeroing a VFP register. + bool HasZeroCycleZeroing; + /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory /// accesses for some types. For details, see /// ARMTargetLowering::allowsUnalignedMemoryAccesses(). @@ -298,6 +302,7 @@ public: bool isFPOnlySP() const { return FPOnlySP; } bool hasPerfMon() const { return HasPerfMon; } bool hasTrustZone() const { return HasTrustZone; } + bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; } bool prefers32BitThumb() const { return Pref32BitThumb; } bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; } |