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| author | Jim Grosbach <grosbach@apple.com> | 2011-11-10 16:44:55 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-11-10 16:44:55 +0000 |
| commit | 71810ab7c0ecd6927dde1eee0c73169642f3764d (patch) | |
| tree | b4e35812e5c5a75d27c73f3c693ca3171e5fe098 /lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
| parent | 977665c24a4f2c0d05774deef607b6a20bc265f2 (diff) | |
| download | llvm-71810ab7c0ecd6927dde1eee0c73169642f3764d.tar.gz llvm-71810ab7c0ecd6927dde1eee0c73169642f3764d.tar.bz2 llvm-71810ab7c0ecd6927dde1eee0c73169642f3764d.tar.xz | |
ARM assembly parsing for ASR(immediate).
Start of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index cb0c97b4c6..e68ecec301 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -4541,6 +4541,21 @@ void ARMAsmParser:: processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { switch (Inst.getOpcode()) { + // Handle the MOV complex aliases. + case ARM::ASRi: { + unsigned Amt = Inst.getOperand(2).getImm() + 1; + unsigned ShiftOp = ARM_AM::getSORegOpc(ARM_AM::asr, Amt); + MCInst TmpInst; + TmpInst.setOpcode(ARM::MOVsi); + TmpInst.addOperand(Inst.getOperand(0)); // Rd + TmpInst.addOperand(Inst.getOperand(1)); // Rn + TmpInst.addOperand(MCOperand::CreateImm(ShiftOp)); // Shift value and ty + TmpInst.addOperand(Inst.getOperand(3)); // CondCode + TmpInst.addOperand(Inst.getOperand(4)); + TmpInst.addOperand(Inst.getOperand(5)); // cc_out + Inst = TmpInst; + break; + } case ARM::LDMIA_UPD: // If this is a load of a single register via a 'pop', then we should use // a post-indexed LDR instruction instead, per the ARM ARM. |