ARM: provide VFP aliases for pre-V6 mnemonics

In order to provide compatibility with the GNU assembler, provide aliases for
pre-UAL mnemonics for floating point operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198172 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 29 insertions, 0 deletions

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index d4122bcb4a..c0e5472346 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5111,6 +5111,15 @@ static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                                     SMLoc NameLoc,
                                SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  // FIXME: Can this be done via tablegen in some fashion?
+  bool HasPrecisionRestrictions;
+  bool AcceptDoublePrecisionOnly;
+  bool AcceptSinglePrecisionOnly;
+  HasPrecisionRestrictions = Name.startswith("fldm") || Name.startswith("fstm");
+  AcceptDoublePrecisionOnly =
+    HasPrecisionRestrictions && (Name.back() == 'd' || Name.back() == 'x');
+  AcceptSinglePrecisionOnly = HasPrecisionRestrictions && Name.back() == 's';
+
   // Apply mnemonic aliases before doing anything else, as the destination
   // mnemonic may include suffices and we want to handle them normally.
   // The generic tblgen'erated code does this later, at the start of
@@ -5279,6 +5288,26 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
 
   Parser.Lex(); // Consume the EndOfStatement
 
+  if (HasPrecisionRestrictions) {
+    ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
+    assert(Op->isRegList());
+    const SmallVectorImpl<unsigned> &RegList = Op->getRegList();
+    for (SmallVectorImpl<unsigned>::const_iterator RLI = RegList.begin(),
+                                                   RLE = RegList.end();
+         RLI != RLE; ++RLI) {
+      if (AcceptSinglePrecisionOnly &&
+          !ARMMCRegisterClasses[ARM::SPRRegClassID].contains(*RLI))
+        return Error(Op->getStartLoc(),
+                     "VFP/Neon single precision register expected");
+      else if (AcceptDoublePrecisionOnly &&
+               !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(*RLI))
+        return Error(Op->getStartLoc(),
+                     "VFP/Neon double precision register expected");
+      else
+        llvm_unreachable("must have single or double precision restrictions");
+    }
+  }
+
   // Some instructions, mostly Thumb, have forms for the same mnemonic that
   // do and don't have a cc_out optional-def operand. With some spot-checks
   // of the operand list, we can figure out which variant we're trying to