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authorSilviu Baranga <silviu.baranga@arm.com>2012-04-18 14:18:57 +0000
committerSilviu Baranga <silviu.baranga@arm.com>2012-04-18 14:18:57 +0000
commit35ee7d28a69173ca0c11fb6b3271518bf4c5bff6 (patch)
tree36cdf572e03f4af86d90597d0ed00c5bbf0727d4 /lib/Target/ARM/Disassembler/ARMDisassembler.cpp
parent6b9f97dd892b0d61d8a1f0ee4f837058f2ca4552 (diff)
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Added support for disassembling unpredictable swp/swpb ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassembler.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 87a5f019d4..912935db17 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -4310,6 +4310,10 @@ static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
DecodeStatus S = MCDisassembler::Success;
+
+ if (Rt == Rn || Rn == Rt2)
+ S = MCDisassembler::SoftFail;
+
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))