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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2011-03-05 18:43:32 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2011-03-05 18:43:32 +0000 |
| commit | 57caad7a33ff145b71545f10dcfbbf2fd0f595d3 (patch) | |
| tree | 6f401503dd439cd105ac56a8c389da865bd9dde9 /lib/Target/ARM/Thumb1FrameLowering.cpp | |
| parent | 94c1b08033b69495387a85124ca888d3c62f78c7 (diff) | |
| download | llvm-57caad7a33ff145b71545f10dcfbbf2fd0f595d3.tar.gz llvm-57caad7a33ff145b71545f10dcfbbf2fd0f595d3.tar.bz2 llvm-57caad7a33ff145b71545f10dcfbbf2fd0f595d3.tar.xz | |
Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb1FrameLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/Thumb1FrameLowering.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/ARM/Thumb1FrameLowering.cpp b/lib/Target/ARM/Thumb1FrameLowering.cpp index 233e165387..5508f6f2aa 100644 --- a/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -39,8 +39,8 @@ static void emitSPUpdate(MachineBasicBlock &MBB, const TargetInstrInfo &TII, DebugLoc dl, const Thumb1RegisterInfo &MRI, int NumBytes) { - emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, - MRI, dl); + emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, + MRI); } void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const { @@ -232,8 +232,8 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, if (NumBytes) { assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && "No scratch register to restore SP from FP!"); - emitThumbRegPlusImmediate(MBB, MBBI, ARM::R4, FramePtr, -NumBytes, - TII, *RegInfo, dl); + emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, + TII, *RegInfo); BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP) .addReg(ARM::R4); } else |