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| author | Craig Topper <craig.topper@gmail.com> | 2012-04-20 07:30:17 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-04-20 07:30:17 +0000 |
| commit | 420761a0f193e87d08ee1c51b26bba23ab4bac7f (patch) | |
| tree | 55aa0936b18927fe72fb4806eeab177b42c2f9cd /lib/Target/ARM/Thumb1InstrInfo.cpp | |
| parent | c909950c384e8234a7b3c5a76b7f79e3f7012ceb (diff) | |
| download | llvm-420761a0f193e87d08ee1c51b26bba23ab4bac7f.tar.gz llvm-420761a0f193e87d08ee1c51b26bba23ab4bac7f.tar.bz2 llvm-420761a0f193e87d08ee1c51b26bba23ab4bac7f.tar.xz | |
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb1InstrInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/Thumb1InstrInfo.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp index e03e75815c..735b255759 100644 --- a/lib/Target/ARM/Thumb1InstrInfo.cpp +++ b/lib/Target/ARM/Thumb1InstrInfo.cpp @@ -53,11 +53,11 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - assert((RC == ARM::tGPRRegisterClass || + assert((RC == &ARM::tGPRRegClass || (TargetRegisterInfo::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) && "Unknown regclass!"); - if (RC == ARM::tGPRRegisterClass || + if (RC == &ARM::tGPRRegClass || (TargetRegisterInfo::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) { DebugLoc DL; @@ -81,11 +81,11 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - assert((RC == ARM::tGPRRegisterClass || + assert((RC == &ARM::tGPRRegClass || (TargetRegisterInfo::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) && "Unknown regclass!"); - if (RC == ARM::tGPRRegisterClass || + if (RC == &ARM::tGPRRegClass || (TargetRegisterInfo::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) { DebugLoc DL; |